公开(公告)号：US11898249B2

公开(公告)日：2024-02-13

申请号：US18108989

申请日：2023-02-13

Applicant: Applied Materials, Inc.

Inventor： Nagarajan Rajagopalan ,  Xinhai Han ,  Michael Wenyoung Tsiang ,  Masaki Ogata ,  Zhijun Jiang ,  Juan Carlos Rocha-Alvarez ,  Thomas Nowak ,  Jianhua Zhou ,  Ramprakash Sankarakrishnan ,  Amit Kumar Bansal ,  Jeongmin Lee ,  Todd Egan ,  Edward W. Budiarto ,  Dmitriy Panasyuk ,  Terrance Y. Lee ,  Jian J. Chen ,  Mohamad A. Ayoub ,  Heung Lak Park ,  Patrick Reilly ,  Shahid Shaikh ,  Bok Hoen Kim ,  Sergey Starik ,  Ganesh Balasubramanian

IPC: C23C16/52 ,  G01B11/06 ,  H01L21/687 ,  H01L21/67 ,  C23C16/509 ,  G01N21/55 ,  G01N21/65 ,  H01L21/00 ,  C23C16/458 ,  C23C16/46 ,  C23C16/50 ,  C23C16/505 ,  C23C16/455

CPC classification number: C23C16/52 ,  C23C16/458 ,  C23C16/4557 ,  C23C16/45565 ,  C23C16/46 ,  C23C16/50 ,  C23C16/505 ,  C23C16/509 ,  C23C16/5096 ,  G01B11/0625 ,  G01B11/0683 ,  G01N21/55 ,  G01N21/658 ,  H01L21/00 ,  H01L21/67248 ,  H01L21/67253 ,  H01L21/687 ,  G01N2201/1222

Abstract: A method of processing a substrate according to a PECVD process is described. Temperature profile of the substrate is adjusted to change deposition rate profile across the substrate. Plasma density profile is adjusted to change deposition rate profile across the substrate. Chamber surfaces exposed to the plasma are heated to improve plasma density uniformity and reduce formation of low quality deposits on chamber surfaces. In situ metrology may be used to monitor progress of a deposition process and trigger control actions involving substrate temperature profile, plasma density profile, pressure, temperature, and flow of reactants.

公开(公告)号：US11889004B2

公开(公告)日：2024-01-30

申请号：US17816315

申请日：2022-07-29

Applicant: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.

Inventor： Martin Koenig

IPC: H04L9/32 ,  G06F21/72 ,  H04L9/08 ,  H01L23/00 ,  H01L21/00 ,  G06F21/75 ,  G06F21/86 ,  H01L49/02

CPC classification number: H04L9/3278 ,  G06F21/72 ,  G06F21/75 ,  G06F21/86 ,  H01L21/00 ,  H01L23/57 ,  H01L23/573 ,  H01L28/60 ,  H04L9/0861 ,  H04L9/0866 ,  H04L2209/12

Abstract: A method for producing a PUF-film includes printing a layer of dielectric material on a film substrate, such that a variable thickness of the layer is obtained by the printing. The method includes arranging a structured electrode layer on the dielectric material such that the structured electrode layer is influenced with respect to an electric measurement value due to the variable thickness.

公开(公告)号：US11846871B2

公开(公告)日：2023-12-19

申请号：US17868018

申请日：2022-07-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hung-Shu Huang ,  Ming Chyi Liu ,  Tung-He Chou

IPC: H04N5/232 ,  G03B13/36 ,  G01S3/00 ,  H01L21/00 ,  G06V10/40 ,  G06V10/75 ,  G06V40/20 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L21/8234 ,  H01L21/3213 ,  H04N23/67 ,  H04N23/45 ,  H04N23/61 ,  H04N23/63 ,  H04N23/69 ,  H04N23/90 ,  H04N23/698 ,  H04N5/262

CPC classification number: G03B13/36 ,  G01S3/00 ,  G06V10/40 ,  G06V10/751 ,  G06V40/20 ,  H01L21/00 ,  H01L21/32139 ,  H01L21/823456 ,  H01L29/4238 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/42384 ,  H01L29/66613 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7835 ,  H01L29/7836 ,  H04N5/2628 ,  H04N23/45 ,  H04N23/61 ,  H04N23/63 ,  H04N23/675 ,  H04N23/69 ,  H04N23/698 ,  H04N23/90

Abstract: Various embodiments of the present disclosure provide a method for forming a recessed gate electrode that has high thickness uniformity. A gate dielectric layer is deposited lining a recess, and a multilayer film is deposited lining the recess over the gate dielectric layer. The multilayer film comprises a gate electrode layer, a first sacrificial layer over the gate dielectric layer, and a second sacrificial layer over the first sacrificial dielectric layer. A planarization is performed into the second sacrificial layer and stops on the first sacrificial layer. A first etch is performed into the first and second sacrificial layers to remove the first sacrificial layer at sides of the recess. A second etch is performed into the gate electrode layer using the first sacrificial layer as a mask to form the recessed gate electrode. A third etch is performed to remove the first sacrificial layer after the second etch.

公开(公告)号：US20230323540A1

公开(公告)日：2023-10-12

申请号：US18208084

申请日：2023-06-09

Applicant: Varian Semiconductor Equipment Associates, Inc.

Inventor： Elaina BABAYAN ,  Sarah WHITE ,  Vijay VENUGOPAL ,  Jonathan BAKKE

IPC: C23C16/52 ,  C23C16/448 ,  H01L21/67 ,  C23C16/455 ,  G05D16/04 ,  G01F1/00 ,  G05D11/13 ,  G05D16/00 ,  H01L21/00 ,  H01L21/66 ,  G05D11/00

CPC classification number: C23C16/52 ,  C23C16/448 ,  H01L21/67253 ,  C23C16/45544 ,  C23C16/45553 ,  G05D16/0402 ,  G01F1/00 ,  G05D16/04 ,  G05D11/132 ,  G05D16/00 ,  H01L21/00 ,  H01L22/00 ,  G05D11/00

Abstract: An apparatus for controlling precursor flow. The apparatus may include a processor; and a memory unit coupled to the processor, including a flux control routine. The flux control routine may be operative on the processor to monitor the precursor flow and may include a flux calculation processor to determine a precursor flux value based upon a change in detected signal intensity received from a cell of a gas delivery system to deliver a precursor.

公开(公告)号：US11768442B2

公开(公告)日：2023-09-26

申请号：US17973221

申请日：2022-10-25

Applicant: ASML NETHERLANDS B.V.

Inventor： Wim Tjibbo Tel ,  Mark John Maslow ,  Koenraad Van Ingen Schenau ,  Patrick Warnaar ,  Abraham Slachter ,  Roy Anunciado ,  Simon Hendrik Celine Van Gorp ,  Frank Staals ,  Marinus Jochemsen

IPC: G06F30/20 ,  G06F30/33 ,  G06F30/398 ,  G03F7/00 ,  G03F1/00 ,  G06T7/00 ,  G21K5/00 ,  H01L21/00 ,  H01L21/66 ,  G06F119/18

CPC classification number: G03F7/70625 ,  G06F30/20 ,  G06T7/0004 ,  H01L22/20 ,  G03F1/00 ,  G06F30/33 ,  G06F30/398 ,  G06F2119/18 ,  G21K5/00 ,  H01L21/00

Abstract: A method including: obtaining an image of at least part of a substrate, wherein the image includes at least one feature of a device being manufactured in a layer on the substrate; obtaining a layout of features associated with a previous layer adjacent to the layer on the substrate; calculating one or more image-related metrics in dependence on: 1) a contour determined from the image including the at least one feature and 2) the layout; and determining one or more control parameters of a lithographic apparatus and/or one or more further processes in a manufacturing process of the device in dependence on the one or more image-related metrics, wherein at least one of the control parameters is determined to modify the geometry of the contour in order to improve the one or more image-related metrics.

公开(公告)号：US11676773B2

公开(公告)日：2023-06-13

申请号：US17518690

申请日：2021-11-04

Applicant: NORTHWESTERN UNIVERSITY

Inventor： Yu Teng Liang ,  Baiju K. Vijayan ,  Kimberly A. Gray ,  Mark C. Hersam

IPC: H01G9/20 ,  C01G23/053 ,  B01J35/00 ,  C01B32/19 ,  C01B32/192 ,  B01J21/18 ,  H01L21/00 ,  B82Y30/00 ,  B82Y40/00 ,  C09D11/52

CPC classification number: H01G9/2022 ,  B01J35/004 ,  B82Y30/00 ,  B82Y40/00 ,  C01B32/19 ,  C01B32/192 ,  C01G23/053 ,  C09D11/52 ,  H01L21/00 ,  B01J21/18 ,  C01P2004/03 ,  C01P2004/04 ,  C01P2004/24 ,  Y02E10/542 ,  Y02P70/50

Abstract: In one aspect of the invention, a dye sensitized solar cell has a counter-electrode including carbon-titania nanocomposite thin films made by forming a carbon-based ink; forming a titania (TiO2) solution; blade-coating a mechanical mixture of the carbon-based ink and the titania solution onto a substrate; and annealing the blade-coated substrate at a first temperature for a first period of time to obtain the carbon-based titania nanocomposite thin films. In certain embodiments, the carbon-based titania nanocomposite thin films may include solvent-exfoliated graphene titania (SEG-TiO2) nanocomposite thin films, or single walled carbon nanotube titania (SWCNT-TiO2) nanocomposite thin films.

公开(公告)号：US20190204381A1

公开(公告)日：2019-07-04

申请号：US16296052

申请日：2019-03-07

Applicant: STMicroelectronics S.r.l.

Inventor： Alberto PAGANI

IPC: G01R31/28 ,  C12Q1/00 ,  H01L21/66 ,  G01R1/067

CPC classification number: G01R31/2891 ,  B06B2201/00 ,  C12Q1/00 ,  C12Q2304/00 ,  C12Q2326/00 ,  G01N1/00 ,  G01R1/06794 ,  G01R11/00 ,  G01R31/2884 ,  H01L21/00 ,  H01L22/34 ,  H01L2221/00 ,  H01L2924/00

Abstract: A sensing structure is presented for use in testing integrated circuits on a substrate. The sensing structure includes a probe region corresponding to a conductive region for connecting to the integrated circuit. A first sensing region at least partially surrounds the probe region. A plurality of sensing elements connects in series such that a first of the plurality of sensing elements has two terminals respectively connected to the first sensing region and the probe region. And a second of the plurality of sensing elements has two terminals respectively connected to the probe region and a first reference potential.

公开(公告)号：US10082535B2

公开(公告)日：2018-09-25

申请号：US15008868

申请日：2016-01-28

Applicant: Ridgetop Group, Inc.

Inventor： Esko O. Mikkola ,  Hans A. R. Manhaeve

IPC: G01R31/00 ,  G01R31/28 ,  H01L21/66 ,  H01L21/00 ,  G01R1/00

CPC classification number: G01R31/2818 ,  G01R1/00 ,  G01R31/2884 ,  H01L21/00 ,  H01L22/34 ,  H01L2221/00

Abstract: A test structure includes a dedicated addressing circuit that allows large numbers of test devices to be tested simultaneously and the measurement signals read out serially for different test devices. The test structure may be configured for wafer, die or package-level testing. The test structure may be integrated on a common die with the test devices in a single package, provided on separate die in a common package, separately packaged chips or in the form of a collection of standard die configured as the test structure. If on separate die, the test and addressing circuitry is fabricated from a more mature fabrication process than that being characterized for the devices under test. The processes being characterized may be unqualified whereas the test circuitry may be fabricated with different and more mature or qualified processes.

公开(公告)号：US20180266016A1

公开(公告)日：2018-09-20

申请号：US15983455

申请日：2018-05-18

Applicant: SunEdison Semiconductor Limited (UEN20133416H)

Inventor： Zheng Lu ,  Gaurab Samanta ,  Tse-Wei Lu ,  Feng-Chien Tsai

IPC: C30B33/02 ,  H01L21/02 ,  C30B15/20 ,  H01L21/00 ,  H01L29/167 ,  C30B29/06 ,  H01L29/32

CPC classification number: C30B33/02 ,  C30B15/203 ,  C30B29/06 ,  H01L21/00 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262

Abstract: Nitrogen-doped CZ silicon crystal ingots and wafers sliced therefrom are disclosed that provide for post epitaxial thermally treated wafers having oxygen precipitate density and size that are substantially uniformly distributed radially and exhibit the lack of a significant edge effect. Methods for producing such CZ silicon crystal ingots are also provided by controlling the pull rate from molten silicon, the temperature gradient and the nitrogen concentration. Methods for simulating the radial bulk micro defect size distribution, radial bulk micro defect density distribution and oxygen precipitation density distribution of post epitaxial thermally treated wafers sliced from nitrogen-doped CZ silicon crystals are also provided.

公开(公告)号：US10056233B2

公开(公告)日：2018-08-21

申请号：US15635410

申请日：2017-06-28

Applicant: Applied Materials, Inc.

Inventor： Xinglong Chen ,  Saurabh Garg ,  Jang-Gyoo Yang

IPC: H01L21/00 ,  H01J37/32 ,  H01L21/02 ,  H01L21/311 ,  C23C16/505 ,  C23C16/455

CPC classification number: H01J37/32422 ,  C23C16/452 ,  C23C16/455 ,  C23C16/45565 ,  C23C16/505 ,  C23C16/517 ,  H01J37/32357 ,  H01J37/3244 ,  H01J37/32449 ,  H01J37/32495 ,  H01J2237/3321 ,  H01J2237/334 ,  H01L21/00 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/31691 ,  H01L21/67017 ,  H01L21/67069 ,  H01L22/26 ,  H01L27/11502 ,  H01L28/55 ,  H01L43/12

Abstract: Embodiments of the disclosure generally relate to a hybrid plasma processing system incorporating a remote plasma source (RPS) unit with a capacitively coupled plasma (CCP) unit for substrate processing. In one embodiment, the hybrid plasma processing system includes a CCP unit, comprising a lid having one or more through holes, and an ion suppression element, wherein the lid and the ion suppression element define a plasma excitation region, a RPS unit coupled to the CCP unit, and a gas distribution plate disposed between the ion suppression element and a substrate support, wherein the gas distribution plate and the substrate support defines a substrate processing region. In cases where process requires higher power, both CCP and RPS units may be used to generate plasma excited species so that some power burden is shifted from the CCP unit to the RPS unit, which allows the CCP unit to operate at lower power.