公开(公告)号：US20130302948A1

公开(公告)日：2013-11-14

申请号：US13947289

申请日：2013-07-22

Applicant: SEAGATE TECHNOLOGY LLC

Inventor： Dadi Setiadi ,  Peter Nicholas Manos ,  Hsing-Kuen Liou ,  Paramasivan Kamatchi Subramanian ,  Young Pil Kim ,  Hyung-Kyu Lee ,  Maroun Georges Khoury ,  Chulmin Jung

IPC: H01L21/8239

CPC classification number: H01L21/8239 ,  H01L21/823487 ,  H01L27/1052 ,  H01L27/228 ,  H01L27/2454 ,  H01L27/2481

Abstract: A memory array includes a base circuitry layer and a plurality of memory array layers stacked sequentially to form the memory array. Each memory array layer is electrically coupled to the base circuitry layer. Each memory array layer includes a plurality of memory units. Each memory unit includes a vertical pillar transistor electrically coupled to a memory cell.

Abstract translation: 存储器阵列包括基本电路层和顺序堆叠以形成存储器阵列的多个存储器阵列层。 每个存储器阵列层电耦合到基极电路层。 每个存储器阵列层包括多个存储器单元。 每个存储单元包括电耦合到存储单元的垂直柱状晶体管。