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    Programming a Memory Cell Using a Dual Polarity Charge Pump
    1.
    发明申请
    Programming a Memory Cell Using a Dual Polarity Charge Pump 有权
    使用双极性电荷泵编程存储单元

    公开(公告)号：US20150213901A1

    公开(公告)日：2015-07-30

    申请号：US14679654

    申请日：2015-04-06

    Applicant: Seagate Technology LLC

    Inventor： YoungPil Kim ,  Dadi Setiadi ,  Wei Tian ,  Antoine Khoueir ,  Rodney V. Bowman

    IPC: G11C16/14 ,  G11C11/56

    CPC classification number: G11C16/14 ,  G11C11/56 ,  G11C11/5628 ,  G11C11/5635 ,  G11C13/0069 ,  G11C13/0097 ,  G11C16/16 ,  G11C2013/0073 ,  G11C2211/5646

    Abstract: Apparatus and method for managing data in a memory, such as but not limited to a flash memory array. In some embodiments, an apparatus includes an array of memory cells and a dual polarity charge pump. The dual polarity charge pump has a positive polarity voltage source which applies a positive voltage to a charge storage device to program a selected memory cell to a first programming state, and a negative polarity voltage source which applies a negative voltage to the charge storage device to program the selected memory cell to a different, second programming state.

    Abstract translation: 用于管理存储器中的数据的装置和方法，诸如但不限于闪存阵列。 在一些实施例中，装置包括存储器单元阵列和双极性电荷泵。 双极性电荷泵具有正极性电压源，其向电荷存储装置施加正电压以将所选择的存储单元编程为第一编程状态;以及负极性电压源，其向电荷存储装置施加负电压 将所选择的存储器单元编程到不同的第二编程状态。

    PROGRAMMABLE RESISTIVE MEMORY CELL WITH SACRIFICIAL METAL
    3.
    发明申请
    PROGRAMMABLE RESISTIVE MEMORY CELL WITH SACRIFICIAL METAL 审中-公开
    具有金属可编程电容性记忆体

    公开(公告)号：US20130228734A1

    公开(公告)日：2013-09-05

    申请号：US13864359

    申请日：2013-04-17

    Applicant: SEAGATE TECHNOLOGY LLC

    Inventor： Venkatram Venkatasamy ,  Ming Sun ,  Dadi Setiadi

    IPC: H01L45/00

    CPC classification number: H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/16 ,  H01L45/1608

    Abstract: Programmable metallization memory cells include an electrochemically active electrode and an inert electrode and an ion conductor solid electrolyte material between the electrochemically active electrode and the inert electrode. A sacrificial metal is disposed between the electrochemically active electrode and the inert electrode. The sacrificial metal has a more negative standard electrode potential than the filament forming metal

    Abstract translation: 可编程金属化存储单元包括在电化学活性电极和惰性电极之间的电化学活性电极和惰性电极以及离子导体固体电解质材料。 牺牲金属设置在电化学活性电极和惰性电极之间。 牺牲金属具有比成丝金属更负的标准电极电位

    Using Different Programming Modes to Store Data to a Memory Cell
    7.
    发明申请
    Using Different Programming Modes to Store Data to a Memory Cell 有权
    使用不同的编程模式将数据存储到存储单元

    公开(公告)号：US20150179268A1

    公开(公告)日：2015-06-25

    申请号：US14136708

    申请日：2013-12-20

    Applicant: Seagate Technology LLC

    Inventor： YoungPil Kim ,  Rodney Virgil Bowman ,  Dadi Setiadi ,  Wei Tian

    IPC: G11C16/14 ,  G11C13/00

    CPC classification number: G11C16/14 ,  G11C11/56 ,  G11C11/5628 ,  G11C13/004 ,  G11C13/0069 ,  G11C16/10 ,  G11C16/3495 ,  G11C2211/5641

    Abstract: Method and apparatus for managing data in a memory, such as a flash memory array. In accordance with some embodiments, a memory cell is provided with a plurality of available programming states to accommodate multi-level cell (MLC) programming. A control circuit stores a single bit logical value to the memory cell using single level cell (SLC) programming to provide a first read margin between first and second available programming states. The control circuit subsequently stores a single bit logical value to the memory cell using virtual multi-level cell (VMLC) programming to provide a larger, second read margin between the first available programming state and a third available programming state.

    Abstract translation: 用于管理诸如闪存阵列的存储器中的数据的方法和装置。 根据一些实施例，存储器单元被提供有多个可用的编程状态以适应多级单元（MLC）编程。 控制电路使用单电平单元（SLC）编程将单个位逻辑值存储到存储器单元，以在第一和第二可用编程状态之间提供第一读取裕度。 控制电路随后使用虚拟多电平单元（VMLC）编程将单个位逻辑值存储到存储器单元，以在第一可用编程状态和第三可用编程状态之间提供较大的第二读取余量。

    VERTICAL TRANSISTOR WITH HARDENING IMPLANTATION
    9.
    发明申请
    VERTICAL TRANSISTOR WITH HARDENING IMPLANTATION 审中-公开
    具有硬化植入的垂直晶体管

    公开(公告)号：US20140097400A1

    公开(公告)日：2014-04-10

    申请号：US14101801

    申请日：2013-12-10

    Applicant: SEAGATE TECHNOLOGY LLC

    Inventor： Young Pil Kim ,  Hyung-Kew Lee ,  Peter Nicholas Manos ,  Chulmin Jung ,  Maroun Georges Khoury ,  Dadi Setiadi

    IPC: H01L45/00

    CPC classification number: H01L45/1233 ,  H01L27/228 ,  H01L27/2454 ,  H01L45/1206

    Abstract: A vertical transistor includes a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer. Each pillar structure forms a vertical pillar transistor having a top surface and a side surface orthogonal to the top surface. Then a hardening ion species is implanted into the vertical pillar transistor top surface. Then the vertical pillar transistor side surface is oxidized to form a side surface oxide layer. The side surface oxide layer is removed to form vertical pillar transistor having rounded side surfaces.

    Abstract translation: 垂直晶体管包括具有从半导体晶片正交延伸的多个柱结构的半导体晶片。 每个柱结构形成具有与顶表面正交的顶表面和侧表面的垂直柱晶体管。 然后将硬化离子物质注入垂直柱晶体管顶表面。 然后，垂直柱状晶体管侧面被氧化，形成侧面氧化层。 去除侧面氧化物层以形成具有圆形侧表面的垂直柱状晶体管。

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