VERTICAL TRANSISTOR WITH HARDENING IMPLANTATION
    2.
    发明申请
    VERTICAL TRANSISTOR WITH HARDENING IMPLANTATION 审中-公开
    具有硬化植入的垂直晶体管

    公开(公告)号:US20140097400A1

    公开(公告)日:2014-04-10

    申请号:US14101801

    申请日:2013-12-10

    CPC classification number: H01L45/1233 H01L27/228 H01L27/2454 H01L45/1206

    Abstract: A vertical transistor includes a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer. Each pillar structure forms a vertical pillar transistor having a top surface and a side surface orthogonal to the top surface. Then a hardening ion species is implanted into the vertical pillar transistor top surface. Then the vertical pillar transistor side surface is oxidized to form a side surface oxide layer. The side surface oxide layer is removed to form vertical pillar transistor having rounded side surfaces.

    Abstract translation: 垂直晶体管包括具有从半导体晶片正交延伸的多个柱结构的半导体晶片。 每个柱结构形成具有与顶表面正交的顶表面和侧表面的垂直柱晶体管。 然后将硬化离子物质注入垂直柱晶体管顶表面。 然后,垂直柱状晶体管侧面被氧化,形成侧面氧化层。 去除侧面氧化物层以形成具有圆形侧表面的垂直柱状晶体管。

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