公开(公告)号：US20230195986A1

公开(公告)日：2023-06-22

申请号：US18010131

申请日：2022-03-09

Applicant: SOUTHEAST UNIVERSITY

Inventor： Peng CAO ,  Kai WANG ,  Tai YANG ,  Wei BAO

IPC: G06F30/367 ,  G06N3/0442 ,  G06N3/045 ,  G06N3/0464

CPC classification number: G06F30/367 ,  G06N3/0442 ,  G06N3/045 ,  G06N3/0464 ,  G06F2119/12

Abstract: Disclosed in the present invention is a method for predicting a delay at multiple corners for a digital integrated circuit, which is applicable to the problem of timing signoff at multiple corners. In the aspect of feature engineering, a path delay relationship at adjacent corners is extracted by using a dilated convolutional neural network (Dilated CNN), and learning is performed by using a bi-directional long short-term memory model (Bi-directional Long Short-Term Memory, BLSTM) to obtain topology information of a path. Finally, prediction results of a path delay at a plurality of corners are obtained by using an output of a multi-gate mixture-of-experts network model (Multi-gate Mixture-of-Experts, MMoE). Compared with a conventional machine learning method, the present invention can achieve prediction with higher precision through more effective feature engineering processing in a case of low simulation overheads, and is of great significance for timing signoff at multiple corners of a digital integrated circuit.

公开(公告)号：US20240265181A1

公开(公告)日：2024-08-08

申请号：US18571727

申请日：2023-01-03

Applicant: SOUTHEAST UNIVERSITY

Inventor： Peng CAO ,  Qianqian SONG ,  Kai WANG

IPC: G06F30/337 ,  G06F119/06

CPC classification number: G06F30/337 ,  G06F2119/06

Abstract: An optimization method for a digital integrated circuit is provided. Under the precondition of satisfying certain timing constraints, circuit-level, path-level and gate cell-level features of a circuit are extracted to construct a leakage power optimization model, and optimization data from commercial circuit optimization tools is used to train the model to predict voltage threshold types of gate cells after circuit optimization, such that the circuit can be optimized by adjusting voltage thresholds of gate cells in a post-routing gate-level netlist, thus realizing the optimization objective of reducing leakage power.

公开(公告)号：US20200185926A1

公开(公告)日：2020-06-11

申请号：US16488059

申请日：2017-11-08

Applicant: STATE GRID TIANJIN ELECTRIC POWER COMPANY ,  STATE GRID CORPORATION OF CHINA ,  SOUTHEAST UNIVERSITY

Inventor： Xianxu HUO ,  Ling JIANG ,  Honglei ZHAO ,  Baoguo ZHAO ,  Xudong WANG ,  Guodong LI ,  Tianchun XIANG ,  Ke XU ,  Yan QI ,  Lei WU ,  Shiqian MA ,  Jingjing YAN ,  Kai WANG ,  Qingshan XU ,  Lu SUN ,  Aidong ZENG

IPC: H02J3/46 ,  H02J7/00 ,  H02J3/32

Abstract: The invention relates to a method for real-time scheduling of multi-energy complementary micro-grids based on a Rollout algorithm, which is technically characterized by comprising the following steps of: Step 1, setting up a moving-horizon Markov decision process model for the real-time scheduling of the multi-energy complementary micro-grids with random new-energy outputs, and establishing constraint conditions for the real-time scheduling; Step 2, establishing a target function of the real-time scheduling; Step 3, dividing a single complete scheduling cycle into a plurality of scheduling intervals, and finding one basic feasible solution meeting the constraint conditions for the real-time scheduling based on a greedy algorithm; and Step 4, finding a solution to the moving-horizon Markov decision process model for the real-time scheduling of the multi-energy complementary micro-grids by using the Rollout algorithm based on the basic feasible solution from Step 3. With the consideration of the fluctuations in the new-energy outputs, the present invention solves the problems of low speed and low efficiency of a traditional algorithm at the same time, enabling high-speed efficient multi-energy complementary micro-grid real-time scheduling.