公开(公告)号：US20040233911A1

公开(公告)日：2004-11-25

申请号：US10794581

申请日：2004-03-05

Applicant: STMICROELECTRONICS LIMITED

Inventor： Matt Morris

IPC: H04L012/28

CPC classification number: H04J3/0632 ,  H04J3/0685

Abstract: A stream processing system is described in which packets of an input stream each include individual timestamps which represent relative delays between the packets. A programmable counter generates continuously count values that are compared with the timestamps in the packet stream. An output controller determines whether or not to release packets from an output port based on the result of the comparison, preferably only releasing packets when the programmable count value equals the timestamp.

Abstract translation: 描述了流处理系统，其中输入流的分组各自包括表示分组之间的相对延迟的各个时间戳。 可编程计数器产生与分组流中的时间戳相比较的连续计数值。 输出控制器基于比较的结果来确定是否从输出端口释放分组，优选地仅当可编程计数值等于时间戳时才释放分组。

公开(公告)号：US20040228342A1

公开(公告)日：2004-11-18

申请号：US10779466

申请日：2004-02-16

Applicant: STMicroelectronics Limited

Inventor： Matt Morris

IPC: H04L012/56

CPC classification number: H04L49/25 ,  H04L49/103

Abstract: The routing of data streams is discussed, and particularly routing one or more incoming streams to one or more output destination ports. The ability to merge incoming streams is discussed so that several low bit rate input packet streams can be merged into a higher bit rate output stream. An assignment data structure identifies for each input stream the or each destination to which it is to be routed, and a packet allocation data structure holds information about the packets and information about the destination of the packets to allow a memory holding the packets to be controlled accordingly.

Abstract translation: 讨论数据流的路由，特别是将一个或多个输入流路由到一个或多个输出目的地端口。 讨论合并输入流的能力，使得几个低比特率输入分组流可以被合并到更高比特率的输出流中。 分配数据结构为每个输入流标识其要路由的每个目的地，并且分组分配数据结构保存关于分组的信息和关于分组的目的地的信息，以允许控制分组的存储器 相应地。