公开(公告)号：US20040263217A1

公开(公告)日：2004-12-30

申请号：US10827675

申请日：2004-04-19

Applicant: STMicroelectronics Limited

Inventor： Matt Hutson ,  Andrew Dellow ,  Tom Ryan ,  Paul Elliott

IPC: H03K003/00

CPC classification number: G06F1/08

Abstract: A clock source selector for selecting either a first clock signal A or a second clock signal B in accordance with a switch request signal includes three retiming circuits each consisting of two clocked flip-flops. The switch request signal is first retimed relative to clock A to give a signal P, is then retimed relative to clock B to give a signal Q, and finally is retimed relative to clock A to give a signal R. Selector circuitry operates such that when signal Q is asserted, the second clock signal B is output, when neither signal P nor signal R, as combined by a NOR gate, are asserted, the first clock signal A is output, and at other times a zero level is output. The clock source selector can be used in an integrated circuit to form a glitch-free multiplexer.

公开(公告)号：US20040257365A1

公开(公告)日：2004-12-23

申请号：US10811481

申请日：2004-03-26

Applicant: STMicroelectronics Limited

Inventor： Mathieu Robart

IPC: G06T015/60

CPC classification number: G06T15/60

Abstract: An image is rendered which includes at least one light source, a first, shadow-casting object with a second, shadow-receiving object located on the side of the first shadow-casting object remote from said at least one light source. A shadow mask is generated which identifies for each of a plurality of pixels on the shadow receiving surface a grey level representing the intensity of shadow in each pixel. The intensity is determined utilizing the distance between the shadow-casting object and the shadow-receiving object.

Abstract translation: 渲染图像，其包括至少一个光源，第一阴影投射对象，其具有位于远离所述至少一个光源的第一阴影投射对象的一侧上的第二影子接收对象。 产生阴影掩模，其对阴影接收表面上的多个像素中的每一个识别代表每个像素中的阴影强度的灰度级。 使用阴影投射对象和阴影接收对象之间的距离来确定强度。

公开(公告)号：US20040223618A1

公开(公告)日：2004-11-11

申请号：US10773089

申请日：2004-02-03

Applicant: STMicroelectronics Limited

Inventor： Andrew Dellow

IPC: H04L009/00

CPC classification number: H04L9/0631 ,  H04L9/0827 ,  H04L2209/601

Abstract: A semiconductor integrated circuit having a plurality of selectable pathways inter-connected to data sources and data destinations; a cryptographic circuit connected to the selectable pathways to selectively receive data from at least one of the data sources, to decrypt or encrypt the data in accordance with a key, and to selectively provide the encrypted or decrypted data to at least one of the data destinations; an instruction interpreter arranged to receive an instruction signal and to generate an output to control the plurality of selectable pathways to select from which of the data sources the cryptographic circuit receives data and to which destination the cryptographic circuit provides data. The instruction interpreter configured such that the instruction signal defines a data pathway that operates in accordance with a rule that limits the data pathway configurations which are selectable.

Abstract translation: 一种具有与数据源和数据目的地相互连接的多个可选路径的半导体集成电路; 连接到所述可选择路径以选择性地从所述数据源中的至少一个数据源接收数据的密码电路，根据密钥对所述数据进行解密或加密，并且选择性地将加密或解密的数据提供给所述数据目的地中的至少一个 ; 指令解释器，被布置为接收指令信号并产生输出以控制多个可选路径，以从密码电路中的哪一个数据源接收数据以及加密电路提供数据的哪个目的地。 指令解释器被配置为使得指令信号定义根据限制可选择的数据路径配置的规则操作的数据通路。

公开(公告)号：US20040160349A1

公开(公告)日：2004-08-19

申请号：US10385202

申请日：2003-03-10

Applicant: STMicroelectronics Limited

Inventor： Arnaud Laflaquiere

IPC: H03M001/66 ,  H03M001/78

CPC classification number: G06J1/00 ,  H03K4/026

Abstract: A ramp generator includes a resistance ladder supplied with a constant current. Switches are closed in sequence on the resistance ladder to generate the ramp voltage. By using control logic to decode the sequence, a looped shift register is used to close the switches.

Abstract translation: 斜坡发生器包括提供恒定电流的电阻梯。 开关按顺序关闭在电阻梯以产生斜坡电压。 通过使用控制逻辑来解码序列，使用循环移位寄存器来关闭开关。

公开(公告)号：US20040030839A1

公开(公告)日：2004-02-12

申请号：US10278772

申请日：2002-10-22

Applicant: STMicroelectronics Limited

Inventor： Trefor Southwell ,  Peter Hedinger

IPC: G06F012/08

CPC classification number: G06F12/0862 ,  G06F2212/1024 ,  G06F2212/502 ,  G06F2212/6026

Abstract: A cache memory comprises a fetch engine arranged to issue fetch requests for accessing data items from locations in a main memory identified by access addresses in a program being executed, a pre-fetch engine controlled to issue pre-fetch requests for speculatively accessing pre-fetch data items from locations in said main memory identified by addresses which are determined as being a number of locations from respective ones of said access addresses, and a calibrator arranged to selectively vary said number of locations.

Abstract translation: 高速缓存存储器包括：提取引擎，被配置为发出用于从正在执行的程序中的访问地址识别的主存储器中的位置访问数据项的提取请求，控制的预取引擎发布用于推测访问预取的预取请求 来自所述主存储器中的位置的数据项，其由被确定为来自所述访问地址的相应位置的位置的数量确定;以及校准器，被配置为选择性地改变所述位置数。

公开(公告)号：US20030161397A1

公开(公告)日：2003-08-28

申请号：US10159954

申请日：2002-05-31

Applicant: STMicroelectronics Limited

Inventor： Victor Watson ,  Jean-Jacques de Jong

IPC: H04N007/12

CPC classification number: H04N19/86 ,  H04N19/42 ,  H04N19/423 ,  H04N19/61

Abstract: A method for performing a reordering operation on a matrix of input data values, the method comprising: loading the data values into a computer store by forming a plurality of data strings, each data string comprising a plurality of data sub-strings and each data sub-string representing at least one of the data values, and storing each data string in a register of the computer store in which its sub-strings are not individually addressable; and performing a series of data reordering steps operating on one or more of said data strings to reorder said data values; the reordering operation being a scan-wise reordering operation.

Abstract translation: 一种用于对输入数据值的矩阵执行重排序操作的方法，所述方法包括：通过形成多个数据串将数据值加载到计算机存储器中，每个数据串包括多个数据子串和每个数据子 - 字符串表示数据值中的至少一个，并将每个数据串存储在其子串不能单独寻址的计算机存储的寄存器中; 以及执行对一个或多个所述数据串进行操作的一系列数据重排序步骤，以重新排列所述数据值; 重排序操作是扫描式重排序操作。

公开(公告)号：US20030154342A1

公开(公告)日：2003-08-14

申请号：US10072814

申请日：2002-02-08

Applicant: STMicroelectronics Limited

Inventor： Trefor Southwell ,  Peter Hedinger ,  Kristen Jacobs

IPC: G06F012/08

CPC classification number: G06F8/4442

Abstract: A memory map evaluation tool is provided which allows a program to be organised in a manner most compatible with use of a cache. This is done by executing a first version of the program according to a first memory map to generate a program counter trace, converting the program counter trace into a specific format and then translating the program counter trace into physical addresses using a memory map to be evaluated, different from the first memory map. Those physical addresses are then used to evaluate the number of likely cache misses using a model of a direct-mapped cache for the memory map under evaluation.

Abstract translation: 提供了一种存储器映射评估工具，其允许以与缓存的使用最相容的方式组织程序。 这是通过根据第一存储器映射执行程序的第一版本来完成的，以生成程序计数器跟踪，将程序计数器跟踪转换成特定格式，然后使用要评估的存储器映射将程序计数器跟踪转换为物理地址 ，与第一个存储器映射不同。 然后，这些物理地址用于使用正在评估的内存映射的直接映射高速缓存的模型来评估可能的高速缓存未命中的数量。

公开(公告)号：US20030076856A1

公开(公告)日：2003-04-24

申请号：US10167242

申请日：2002-06-11

Applicant: STMicroelectronics Limited

Inventor： Rodrigo Cordero ,  Patrice Woodward

IPC: H04J003/16

CPC classification number: H04N21/42615 ,  H04N21/426 ,  H04N21/434 ,  H04N21/4341 ,  H04N21/4345

Abstract: A receiver for receiving a data stream comprises a filtering arrangement for filtering said received data stream and a processor. The filtering arrangement is arranged to load at least a part of said data stream, to filter at least part of said data stream and to read at least part of said data stream. The filtering arrangement has a first mode in which said steps are carried out and a second mode in which said processor is arranged to interrupt the steps carried out by said filtering arrangement.

Abstract translation: 用于接收数据流的接收机包括用于过滤所述接收的数据流的过滤装置和处理器。 滤波装置被布置为加载所述数据流的至少一部分，以过滤所述数据流的至少一部分并读取所述数据流的至少一部分。 滤波装置具有执行所述步骤的第一模式和其中所述处理器被布置为中断由所述滤波装置执行的步骤的第二模式。

公开(公告)号：US20030001555A1

公开(公告)日：2003-01-02

申请号：US10161077

申请日：2002-05-31

Applicant: STMicroelectronics Limited

Inventor： Peter Johnson

IPC: G05F003/16 ,  G05F003/20

CPC classification number: G05F3/30

Abstract: A current source using a bandgap voltage circuit includes a current gain circuit between the output of the bandgap circuit and the current output transistor. On-off control is provided by a switchable bias circuit providing an ON potential to start the bandgap and a clamping circuit opening the feedback loop.

Abstract translation: 使用带隙电压电路的电流源包括在带隙电路的输出和电流输出晶体管之间的电流增益电路。 开关控制由提供导通电位的可切换偏置电路提供以启动带隙，以及钳位电路打开反馈回路。

公开(公告)号：US20020170041A1

公开(公告)日：2002-11-14

申请号：US10032155

申请日：2001-12-20

Applicant: STMicroelectronics Limited

Inventor： Richard Shann

IPC: G06F009/45

CPC classification number: G06F8/54

Abstract: A method of forming an executable program from a plurality of object code modules, each object code module having section data, a set of relocation instructions and one or more symbols, each symbol having a plurality of attributes associated therewith, wherein said relocation instructions includes a data retrieval instruction having a symbol field identifying a symbol and an attribute field identifying a symbol attribute associated with said identified symbol to be retrieved, the method includes: reading at least one relocation from said set of relocations instruction and where said relocation instruction is a data retrieval instruction, determining the symbol identified by the symbol field and retrieving one of said plurality of symbol attributes associated with said symbol in dependence on the contents of the symbol attributes field of said instruction.

Abstract translation: 一种从多个目标代码模块形成可执行程序的方法，每个目标代码模块具有分段数据，一组重定位指令和一个或多个符号，每个符号具有与之相关联的多个属性，其中所述重定位指令包括 具有标识符号的符号字段的数据检索指令和标识与要检索的所述识别符号相关联的符号属性的属性字段，所述方法包括：从所述重定位指令集中读取至少一个重定位，并且其中所述重定位指令是数据 检索指令，确定符号字段识别的符号，并根据所述指令的符号属性字段的内容，检索与所述符号相关联的所述多个符号属性中的一个。