公开(公告)号：US11973696B2

公开(公告)日：2024-04-30

申请号：US17588385

申请日：2022-01-31

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Niv Aibester ,  Barak Gafni

IPC: H04L49/103 ,  H04L45/122 ,  H04L47/30 ,  H04L49/9005 ,  H04L49/9047

CPC classification number: H04L49/103 ,  H04L45/122 ,  H04L47/30 ,  H04L49/9005 ,  H04L49/9047

Abstract: A network device includes one or more ports, a packet processor, and a memory management circuit. The one or more ports are to communicate packets over a network. The packet processor is to process the packets using a plurality of queues. The memory management circuit is to maintain a shared buffer in a memory and adaptively allocate memory resources from the shared buffer to the queues, to maintain in the memory, in addition to the shared buffer, a shared-reserve memory pool for use by a defined subset of the queues, to identify in the subset a queue that (i) requires additional memory resources, (ii) is not eligible for additional allocation from the shared buffer, and (iii) meets an eligibility condition for the shared-reserve memory pool, and to allocate memory resources to the identified queue from the shared-reserve memory pool.

公开(公告)号：US20240039871A1

公开(公告)日：2024-02-01

申请号：US17816209

申请日：2022-07-29

Applicant: Cisco Technology, Inc.

Inventor： Harsha BHARADWAJ

IPC: H04L49/55 ,  H04L49/103 ,  H04L67/1097

CPC classification number: H04L49/555 ,  H04L49/103 ,  H04L67/1097

Abstract: First Burst (FB) emulation for a FB enabled host at a network switch is described. The FB write operation is an accelerated write input/output (I/O) method for fibre channel non-volatile memory express (NVMe) (FC-NVMe) traffic that reduces a number of communication phases between a host point and storage point. In some examples, a storage system connected to the FB enabled host, via the network switch, is not FB enabled. In this example, the network switch initiates a FB emulation to provide FB functions to the FB enabled host. The FB emulation at the network switch stores FB data from the host as emulated data at the network switch and then transfers the emulated data to the connected storage system using standard write I/O operations.

公开(公告)号：US20230412523A1

公开(公告)日：2023-12-21

申请号：US18460264

申请日：2023-09-01

Applicant: Cisco Technology, Inc.

Inventor： Vinod Mitulal ,  Krishnan Subramani ,  Peter Newman ,  Georges Akis

IPC: H04L49/103 ,  H04L49/00 ,  H04L49/104 ,  H04L47/10 ,  H04L47/32 ,  H04L47/30 ,  H04L49/9005 ,  H04L49/90

CPC classification number: H04L49/103 ,  H04L49/3036 ,  H04L49/108 ,  H04L47/29 ,  H04L47/32 ,  H04L47/30 ,  H04L49/9005 ,  H04L49/9084

Abstract: The subject technology relates to the management of a shared buffer memory in a network switch. Systems, methods, and machine readable media are provided for receiving a data packet at a first network queue from among a plurality of network queues, determining if a fill level of a queue in a shared buffer of the network switch exceeds a dynamic queue threshold, and in an event that the fill level of the shared buffer exceeds the dynamic queue threshold, determining if a fill level of the first network queue is less than a static queue minimum threshold.

公开(公告)号：US11671382B2

公开(公告)日：2023-06-06

申请号：US15185864

申请日：2016-06-17

Applicant: Intel Corporation

Inventor： John J. Browne ,  Seán Harte ,  Tomasz Kantecki ,  Pierre Laurent ,  Chris MacNamara

IPC: H04N21/443 ,  H04L49/9057 ,  H04N21/426 ,  H04L49/103 ,  H04L1/00 ,  H04L49/102 ,  H04L49/00 ,  H04L49/9005 ,  H04N21/232

CPC classification number: H04L49/9057 ,  H04L1/0016 ,  H04L49/102 ,  H04L49/103 ,  H04L49/3063 ,  H04N21/42692 ,  H04N21/4435 ,  H04L1/002 ,  H04L49/9005 ,  H04N21/2326

Abstract: Technologies for coordinating access to packets include a network device. The network device is to establish a ring in a memory of the network device. The ring includes a plurality of slots. The network device is also to allocate cores to each of an input stage, an output stage, and a worker stage. The worker stage is to process data in a data packet with an associated worker function. The network device is also to add, with the input stage, an entry to a slot in the ring representative of a data packet received with a network interface controller of the network device, access, with the worker stage, the entry in the ring to process at least a portion of the data packet, and provide, with the output stage, the processed data packet to the network interface controller for transmission.

公开(公告)号：US10009293B1

公开(公告)日：2018-06-26

申请号：US15282883

申请日：2016-09-30

Applicant: Juniper Networks, Inc.

Inventor： Dev S. Mukherjee ,  Marco Rodriguez ,  Sarin Thomas ,  Gary Goldman

IPC: H04L12/933 ,  H04L12/741 ,  H04L12/947

CPC classification number: H04L49/103 ,  H04L45/74 ,  H04L49/25

Abstract: A system and method of transferring cells through a router includes writing one or more of the plurality of cells, including a first cell, of a packet from an ingress stream of an ingress writer to a central buffer, storing a packet identifier entry in the first egress reader scoreboard in each of the plurality of egress readers, the packet identifier entry including a packet identifier, a valid bit, a hit bit and a write cell count, wherein the valid bit is configured to indicate that the packet identifier entry is valid, the hit bit is configured to indicate that no cells in the packet have been read from the central buffer and the write cell count equals the number of cells in the packet written to the central buffer, and reading the packet from the central buffer as a function of the packet identifier entry.

公开(公告)号：US20170337010A1

公开(公告)日：2017-11-23

申请号：US15161316

申请日：2016-05-23

Applicant: Mellanox Technologies TLV Ltd.

Inventor： Roy Kriss ,  Barak Gafni ,  George Elias ,  Eran Rubinstein ,  Shachar Bar Tikva

IPC: G06F3/06 ,  H04L12/933

CPC classification number: G06F3/0656 ,  G06F3/061 ,  G06F3/0631 ,  G06F3/067 ,  H04L49/103 ,  H04L49/3036 ,  H04L49/9036

Abstract: Communication apparatus includes multiple ports configured to serve as ingress ports and egress ports for connection to a packet data network. A memory is coupled to the ports and configured to contain both respective input buffers allocated to the ingress ports and a shared buffer holding data packets for transmission in multiple queues via the egress ports. Control logic is configured to monitor an overall occupancy level of the memory, and when a data packet is received through an ingress port having an input buffer that is fully occupied while the overall occupancy level of the memory is below a specified maximum, to allocate additional space in the memory to the input buffer and to accept the received data packet into the additional space.

公开(公告)号：US20170295112A1

公开(公告)日：2017-10-12

申请号：US15531694

申请日：2014-12-24

Applicant: Intel Corporation

Inventor： Albert S. CHENG ,  Thomas D. LOVETT ,  Michael S. PARKER ,  Steven F. HOOVER

IPC: H04L12/935 ,  H04L12/937

CPC classification number: H04L49/3036 ,  H04L12/6418 ,  H04L49/101 ,  H04L49/103 ,  H04L49/254 ,  H04L49/505 ,  H04L49/9036

Abstract: Apparatuses, methods and storage medium associated with buffering data in a switch are provided. In embodiments, the switch may include a plurality of queue buffers, a plurality of queues respectively associated with the plurality of queue buffers, a shared buffer, and a queue point controller coupled with the plurality of queue buffers and the shared buffer. In embodiments the queue point controller may be configured to determine an amount of available space in a selected queue buffer of the plurality of queue buffers. The queue point controller may be further configured to allocate at least a portion of the shared buffer to a selected queue that is associated with the selected queue buffer. In embodiments, this allocation may be based on the amount of available space determined in the selected queue buffer. Other embodiments may be described and/or claimed.

公开(公告)号：US09660835B2

公开(公告)日：2017-05-23

申请号：US14540901

申请日：2014-11-13

Applicant: LSIS CO., LTD.

Inventor： Sung Sik Ham

IPC: H04L12/28 ,  H04L12/64 ,  H04L12/865 ,  H04L12/935 ,  H04L12/933

CPC classification number: H04L12/6418 ,  H04L47/6275 ,  H04L49/103 ,  H04L49/3036

Abstract: Disclosed is a bidirectional packet transfer fail-over switch for serial communication. The bidirectional packet transfer fail-over switch for serial communication includes a memory configured to divide packet data, which is transmitted or received for bidirectional communication between a plurality of communication devices, in units of certain data, and store the divided data, and a control unit configured to receive a trigger signal, indicating whether the packet data is received, from the memory, determine a priority according to an order where the packet data is received, and transmit the packet data to another communication device.

公开(公告)号：US09602568B2

公开(公告)日：2017-03-21

申请号：US14822816

申请日：2015-08-10

Applicant: BROADCOM CORPORATION

Inventor： Rajesh Shankarrao Mamidwar ,  Sanjeev Sood ,  Anand Tongle ,  David Wu ,  Prashant Katre

IPC: G06F15/16 ,  H04L29/06 ,  H04L29/08 ,  H04L12/931 ,  H04L12/70 ,  H04L12/933 ,  H04L12/861 ,  H04L1/18 ,  H04L12/883 ,  H04L12/64 ,  H04L12/879

CPC classification number: H04L65/604 ,  H04L1/1874 ,  H04L49/103 ,  H04L49/206 ,  H04L49/35 ,  H04L49/9021 ,  H04L49/9026 ,  H04L49/9036 ,  H04L49/9047 ,  H04L65/607 ,  H04L67/32 ,  H04L2012/5678 ,  H04L2012/5681 ,  H04L2012/6489

Abstract: A system for adaptive audio video (AV) stream processing may include at least one processor and a switch device. The switch device may be configured to route AV traffic to the processor, and to receive AV traffic from the processor and provide the AV traffic to a client device via one or more channels. The processor may monitor a transcoder buffer depth and depths of buffers associated with channels over which the AV traffic is being transmitted. The processor may adaptively modify one or more attributes associated with the AV traffic based at least on the monitored buffer depths. For example, the processor may adaptively adjust a bit rate associated with transcoding the AV traffic based at least on the transcoder buffer depth. The processor may utilize the depths of the buffers associated with the channels to adaptively adjust the amount of AV traffic provided for transmission over the channels.

公开(公告)号：US20160232126A1

公开(公告)日：2016-08-11

申请号：US15019234

申请日：2016-02-09

Applicant: FTS Computertechnik GmbH

Inventor： Stefan POLEDNA ,  Hermann KOPETZ ,  Martin SCHWARZ

IPC: G06F15/173 ,  H04L29/08

CPC classification number: G06F15/17331 ,  G06F12/0835 ,  G06F12/1081 ,  H04L49/103 ,  H04L49/35 ,  H04L67/10

Abstract: The invention relates to a method for processing real-time data in a distribution unit of a distributed computer system, the computer system comprising a plurality of node computers and distribution units, the distribution unit containing, in addition to a switching engine (SE) and a switching memory (SM), one or more application computers each with one or more application central processing units and each with one or more application memories (AM), wherein the switching engine of the distribution unit, when it receives, at one of its ports, a message intended for an application computer, forwards this message to the addressed application computer through a direct memory access (DMA) unit that is arranged between the switching memory and the application memory of the addressed application computer and that is under the control of the switching engine. The invention also relates to an expanded distribution unit and a computer system with such expanded distribution units.

Abstract translation: 本发明涉及一种用于处理分布式计算机系统的分发单元中的实时数据的方法，所述计算机系统包括多个节点计算机和分配单元，所述分配单元除了包括切换引擎（SE）和 切换存储器（SM），一个或多个应用计算机，每个应用计算机具有一个或多个应用中央处理单元，并且每个应用计算机具有一个或多个应用存储器（AM），其中分发单元的交换引擎在接收到其中一个应用存储器 端口，用于应用计算机的消息，通过直接存储器访问（DMA）单元将该消息转发到寻址的应用计算机，所述直接存储器访问（DMA）单元布置在交换存储器和所寻址的应用计算机的应用存储器之间，并且处于 交换引擎。 本发明还涉及一种具有这种扩展分配单元的扩展分配单元和计算机系统。