公开(公告)号：US20220103201A1

公开(公告)日：2022-03-31

申请号：US17480926

申请日：2021-09-21

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Lucia MAGGIO ,  Marzia ANNOVAZZI ,  Diego ALAGNA

IPC: H04B1/44

Abstract: A communication system has a galvanic isolation link coupling a first circuit to a second circuit. The first circuit transmits first data signals to the second circuit and receives second data signals from the second circuit in response to the first data signals. The data signals are transmitted in consecutive time slots of a determined time duration via the galvanic isolation link. The first data signals include polling signals transmitted from the first circuit to the second circuit during consecutive time slots, and on-demand access requests transmitted from the first circuit to the second circuit. The second data signals include status response signals transmitted from the second circuit to the first circuit in response to polling signals received from the first circuit, and access response signals transmitted from the second circuit to the first circuit in response to access requests received from the first circuit.

公开(公告)号：US20230393198A1

公开(公告)日：2023-12-07

申请号：US18324583

申请日：2023-05-26

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Diego ALAGNA ,  Alessandro CANNONE

IPC: G01R31/3177 ,  G01R31/317 ,  G06F1/08

CPC classification number: G01R31/3177 ,  G06F1/08 ,  G01R31/31725

Abstract: A first circuit is coupled to a second circuit via a communication link. The first circuit generates a first validation signal, a second validation signal, and control signals, and transmits the first and second validation signals to the second circuit via the communication link. The second circuit validates the control signals based on the first and second binary validation signals. The validating includes: verifying that when the first validation signal has a first value, the second validation signal has a second value different from the first value; verifying that when the second validation signal has the first value, the first validation signal has the second value; verifying detection of a transition edge of the first validation signal within a threshold number of clock cycles; and verifying detection of a transition edge of the second validation signal within the threshold number of clock cycles.

公开(公告)号：US20230266381A1

公开(公告)日：2023-08-24

申请号：US17678763

申请日：2022-02-23

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Gaudenzia BAGNATI ,  Marzia ANNOVAZZI ,  Diego ALAGNA ,  Lucia MAGGIO

IPC: G01R31/28 ,  H03K17/687 ,  H03K21/08 ,  H03K5/24

CPC classification number: G01R31/2851 ,  H03K17/6874 ,  H03K21/08 ,  H03K5/24 ,  G01R31/52

Abstract: An integrated circuit includes a plurality of power transistor driver channels for driving external loads. The driver channels can be selectively configured as high side or low side driver channels. The integrated circuit includes, for each driver channel, a respective analog test circuit and a respective controller. The integrated circuit includes a single counter connected to each of the controllers for simultaneously controlling off-state diagnosis timing windows for the driver channels.