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公开(公告)号：US20190214910A1
公开(公告)日：2019-07-11
申请号：US16222557
申请日：2018-12-17
Inventor： Matthieu Thomas , Michele Suraci , Massimo Mazzucco
IPC: H02M3/158
CPC classification number: H02M3/1582 , H02M1/08 , H02M3/1584 , H02M3/1588 , H02M2001/0006 , H02M2001/0009
Abstract: A DC-DC converter circuit including at least: a first step down converter having a first pair of switching devices in a half bridge configuration. A second step down converter includes a second pair of switching devices in a half bridge configuration. The first and second step down converters are connected in parallel to an output node connected to an output coil and receive command signals. A feedback loop includes a synchronization module receiving the gate control signals of high side switching devices and adjusts as a function of the gate control signals a delay in a signal path from the command signal to each gate control signal of the high side switching device to synchronize the gate control signals.
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公开(公告)号：US10720840B2
公开(公告)日：2020-07-21
申请号：US16222557
申请日：2018-12-17
Inventor： Matthieu Thomas , Michele Suraci , Massimo Mazzucco
Abstract: A DC-DC converter circuit including at least: a first step down converter having a first pair of switching devices in a half bridge configuration. A second step down converter includes a second pair of switching devices in a half bridge configuration. The first and second step down converters are connected in parallel to an output node connected to an output coil and receive command signals. A feedback loop includes a synchronization module receiving the gate control signals of high side switching devices and adjusts as a function of the gate control signals a delay in a signal path from the command signal to each gate control signal of the high side switching device to synchronize the gate control signals.
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公开(公告)号：US09712060B2
公开(公告)日：2017-07-18
申请号：US15087082
申请日：2016-03-31
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Paolo Pulici , Massimo Mazzucco
CPC classification number: H02M3/1584 , G05F1/46 , H02M1/08 , H02M3/156 , H02M2001/0025 , H02M2001/008
Abstract: A method manages hysteretic DC-DC buck converters each including a hysteretic comparator operating according to a respective hysteresis window. The method includes, in a given converter, verifying if a respective feedback voltage reaches a lower threshold in order to enter a switch-on period of the converter, The method comprises: while the verifying indicates that the lower threshold is not reached, detecting if another converter has entered a respective switch on period and, in the affirmative, entering a hysteresis voltage adjustment procedure, include increasing by a given amount the amplitude of the hysteresis window of the given converter by reducing the lower threshold of the hysteresis window.
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公开(公告)号：US20170085180A1
公开(公告)日：2017-03-23
申请号：US15087082
申请日：2016-03-31
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Paolo Pulici , Massimo Mazzucco
CPC classification number: H02M3/1584 , G05F1/46 , H02M1/08 , H02M3/156 , H02M2001/0025 , H02M2001/008
Abstract: A method manages hysteretic DC-DC buck converters each including a hysteretic comparator operating according to a respective hysteresis window. The method includes, in a given converter, verifying if a respective feedback voltage reaches a lower threshold in order to enter a switch-on period of the converter, The method comprises: while the verifying indicates that the lower threshold is not reached, detecting if another converter has entered a respective switch on period and, in the affirmative, entering a hysteresis voltage adjustment procedure, include increasing by a given amount the amplitude of the hysteresis window of the given converter by reducing the lower threshold of the hysteresis window.
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