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公开(公告)号：US11946958B2
公开(公告)日：2024-04-02
申请号：US17655891
申请日：2022-03-22
Applicant: STMicroelectronics S.r.l.
Inventor： Paolo Angelini
CPC classification number: G01R19/25 , G01R15/146
Abstract: In accordance with an embodiment, a method of measuring a load current flowing through a current measurement resistor coupled between a source node and a load node includes: measuring a first voltage across a replica resistor when a first end of the replica resistor is coupled to the source node and a second end of the replica resistor is coupled to a reference current source; measuring a second voltage across the replica resistor when the second end of the replica resistor is coupled to the source node and the first end of the replica resistor is coupled to the reference current source; measure a third voltage across the current sensing resistor; and calculating a corrected current measurement of the load current based on the measured first voltage, the measured second voltage and the measured third voltage.
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公开(公告)号：US20220357375A1
公开(公告)日：2022-11-10
申请号：US17655891
申请日：2022-03-22
Applicant: STMicroelectronics S.r.l.
Inventor： Paolo Angelini
Abstract: In accordance with an embodiment, a method of measuring a load current flowing through a current measurement resistor coupled between a source node and a load node includes: measuring a first voltage across a replica resistor when a first end of the replica resistor is coupled to the source node and a second end of the replica resistor is coupled to a reference current source; measuring a second voltage across the replica resistor when the second end of the replica resistor is coupled to the source node and the first end of the replica resistor is coupled to the reference current source; measure a third voltage across the current sensing resistor; and calculating a corrected current measurement of the load current based on the measured first voltage, the measured second voltage and the measured third voltage.
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公开(公告)号：US11075580B2
公开(公告)日：2021-07-27
申请号：US16849034
申请日：2020-04-15
Applicant: STMicroelectronics S.r.l.
Inventor： Roberto Pio Baorda , Stefano Ramorini , Paolo Angelini
Abstract: A sensor comprises a first transistor comprising a first control terminal, a second transistor that is a scaled version of and connected to the first transistor and comprising a second control terminal, an operational amplifier connected to both the first and second transistors and configured to generate an intermediate signal at an output terminal, a variable current source, a current mirror, a measurement circuit, and a chopper circuit. The first and second control terminals are configured to receive a drive signal. The variable current source is configured to generate a first variable current as a function of the intermediate signal. The current mirror configured to apply a second variable current proportional to the first variable current to the second transistor. The measurement circuit is configured to generate a measurement signal indicative of current through the first transistor. The chopper circuit is configured to shift an offset of the operation amplifier.
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公开(公告)号：US09389256B2
公开(公告)日：2016-07-12
申请号：US13717780
申请日：2012-12-18
Inventor： Paolo Angelini , Giovanni Carlo Tripoli , Ernesto Lasalandra , Tommaso Ungaretti , Kien Beng Tan , Yannick Guedon , Dianbo Guo , Sze-Kwang Tan
CPC classification number: G01R27/2605 , G06F3/0418 , G06F3/044
Abstract: Capacitance sensing circuits and methods are provided. The capacitance sensing circuit includes a capacitance-to-voltage converter configured to receive a signal from a capacitance to be sensed and to provide an output signal representative of the capacitance, an output chopper configured to convert the output signal of the capacitance-to-voltage converter to a sensed voltage representative of the capacitance to be sensed, an analog accumulator configured to accumulate sensed voltages during an accumulation period of NA sensing cycles and to provide an accumulated analog value, an amplifier configured to amplify the accumulated analog value, and an analog-to-digital converter configured to convert the amplified accumulated analog value to a digital value representative of the capacitance to be sensed. The analog accumulator may include a low pass filter having a frequency response to filter wideband noise.
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公开(公告)号：US20140292375A1
公开(公告)日：2014-10-02
申请号：US13853870
申请日：2013-03-29
Inventor： Paolo Angelini , Yannick Guedon , Ming Zi Zhu
IPC: G11C27/02
CPC classification number: G06F3/044 , G03G7/00 , G06F3/0418 , G06G7/00
Abstract: Accumulators that operate to fully or partially remove noise from a signal, including removing noise inserted into the signal by the accumulator itself. In some embodiments, an accumulator may be operated in a sampling phase and a transfer phase each time the accumulator samples an input signal. In some such embodiments, an op-amp of an accumulation circuit of the accumulator may be auto-zeroed during some or all of the sampling phases of an accumulation period. In some embodiments in which the op-amp is auto-zeroed during some or all of the sampling phases, the accumulation circuit may include a holding capacitor that, during an auto-zeroing process, holds a value output by the op-amp during a prior transfer phase. Including such a holding capacitor in an accumulator may reduce a voltage that the op-amp output rises following the auto-zero process, which may reduce a bandwidth and noise of the accumulation circuit.
Abstract translation: 用于完全或部分地从信号中去除噪声的累加器，包括消除蓄电池本身插入到信号中的噪声。 在一些实施例中，每当累加器对输入信号进行采样时，累加器可以在采样阶段和传送阶段中操作。 在一些这样的实施例中，累加器的累加电路的运算放大器可以在累积周期的某些或全部采样阶段期间自动归零。 在一些实施例中，在某些或所有采样相位期间运算放大器自动归零，其中累积电路可以包括保持电容器，其在自动归零过程期间保持由运算放大器输出的值 先前转移阶段。 在存储器中包括这种保持电容器可以降低运算放大器输出在自动归零过程之后上升的电压，这可以降低积累电路的带宽和噪声。
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Patent Agency Ranking
6.发明授权公开(公告)号：US10788920B2
公开(公告)日：2020-09-29
申请号：US15797814
申请日：2017-10-30
Applicant: STMicroelectronics S.r.l.
Inventor： Roberto Pio Baorda , Paolo Angelini , Danilo Karim Kaddouri
Abstract: A differential current conveyor circuit includes two or more single-ended current conveyor stages and a common bias stage. First and second switches are set between the control terminals of the transistors in the common bias stage and a respective one of a first and a second coupling line of the single ended stages can be switched between the following: a reset state of the circuit with the transistors in the common bias stage coupled to the first and second coupling lines with the single-ended stages set to a bias condition; and a sensing state of the circuit with the transistors in the common bias stage decoupled from the first and second coupling lines, with the single-ended stages in a high impedance state with the control terminals of the input transistors of the single ended stages capacitively coupled to the input terminal.
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公开(公告)号：US09235300B2
公开(公告)日：2016-01-12
申请号：US13853870
申请日：2013-03-29
Inventor： Paolo Angelini , Yannick Guedon , Ming Zi Zhu
CPC classification number: G06F3/044 , G03G7/00 , G06F3/0418 , G06G7/00
Abstract: Accumulators that operate to fully or partially remove noise from a signal, including removing noise inserted into the signal by the accumulator itself. In some embodiments, an accumulator may be operated in a sampling phase and a transfer phase each time the accumulator samples an input signal. In some such embodiments, an op-amp of an accumulation circuit of the accumulator may be auto-zeroed during some or all of the sampling phases of an accumulation period. In some embodiments in which the op-amp is auto-zeroed during some or all of the sampling phases, the accumulation circuit may include a holding capacitor that, during an auto-zeroing process, holds a value output by the op-amp during a prior transfer phase. Including such a holding capacitor in an accumulator may reduce a voltage that the op-amp output rises following the auto-zero process, which may reduce a bandwidth and noise of the accumulation circuit.
Abstract translation: 用于完全或部分地从信号中去除噪声的累加器，包括消除蓄电池本身插入到信号中的噪声。 在一些实施例中，每当累加器对输入信号进行采样时，累加器可以在采样阶段和传送阶段中操作。 在一些这样的实施例中，累加器的累加电路的运算放大器可以在累积周期的某些或全部采样阶段期间自动归零。 在一些实施例中，在某些或所有采样相位期间运算放大器自动归零，其中累积电路可以包括保持电容器，其在自动归零过程期间保持由运算放大器输出的值 先前转移阶段。 在存储器中包括这种保持电容器可以降低运算放大器输出在自动归零过程之后上升的电压，这可以降低积累电路的带宽和噪声。
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8.发明授权Switched-capacitor band-pass filter of a discrete-time type, in particular for cancelling offset and low-frequency noise of switched-capacitor stages 有权离散时间类型的开关电容带通滤波器，特别是用于消除开关电容器级的偏移和低频噪声公开(公告)号：US09106208B2
公开(公告)日：2015-08-11
申请号：US13928024
申请日：2013-06-26
Applicant: STMicroelectronics S.r.l.
Inventor： Andrea Visconti , Luciano Prandi , Carlo Caminada , Paolo Angelini
CPC classification number: H03H11/126 , H03H19/004
Abstract: A band-pass filter made up by an operational amplifier and by an input circuit. The input circuit is formed by a capacitive filtering element, connected to the input of the operational amplifier; a coupling switch, coupled between an input node and the capacitive filtering element; a capacitive sampling element, coupled between the input of the filter and the input node; and a sampling switch, coupled between the input node and a reference-potential line. The coupling switch and the input sampling switch close in phase opposition according to a succession of undesired components sampling and sensing steps, so that the capacitive sampling element forms a sampler for sampling the undesired component in the undesired components sampling step, in the absence of the component of interest, and forms a subtractor of the undesired components from the input signal in the sensing step.
Abstract translation: 由运算放大器和输入电路构成的带通滤波器。 输入电路由电容滤波元件形成，连接到运算放大器的输入端; 耦合开关，耦合在输入节点和电容滤波元件之间; 耦合在滤波器的输入端和输入节点之间的电容性采样元件; 以及耦合在输入节点和参考电位线之间的采样开关。 耦合开关和输入采样开关根据一系列不期望的分量采样和感测步骤接近相位，使得电容采样元件形成采样器，用于在不期望的分量采样步骤中采样不期望的分量，在不存在 并且在感测步骤中从输入信号形成不期望的分量的减法器。
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9.发明授权Configurable analog front-end for mutual capacitance sensing and self capacitance sensing 有权可配置的模拟前端，用于互电容感测和自电容感测公开(公告)号：US08976151B2
公开(公告)日：2015-03-10
申请号：US13717766
申请日：2012-12-18
Inventor： Kien Beng Tan , Ernesto Lasalandra , Tommaso Ungaretti , Yannick Guedon , Dianbo Guo , Paolo Angelini , Giovanni Carlo Tripoli
CPC classification number: G01R27/2605 , G06F3/0416 , G06F3/044 , G06F2203/04104
Abstract: Capacitance sensing circuits and methods are provided. A dual mode capacitance sensing circuit includes a capacitance-to-voltage converter having an amplifier and an integration capacitance coupled between an output and an inverting input of the amplifier, and a dual mode switching circuit responsive to mutual mode control signals for a controlling signal supplied from a capacitive touch matrix to the capacitance-to-voltage converter in a mutual capacitance sensing mode and responsive to self mode control signals for controlling signals supplied from the capacitive touch matrix to the capacitance-to-voltage converter in a self capacitance sensing mode, wherein the capacitance sensing circuit is configurable for operation in the mutual capacitance sensing mode or the self capacitance sensing mode.
Abstract translation: 提供电容感测电路和方法。 双模电容感测电路包括具有放大器和耦合在放大器的输出和反相输入端之间的积分电容器的电容 - 电压转换器，以及响应于所提供的控制信号的相互模式控制信号的双模式切换电路 在互电容感测模式中从电容式触摸矩阵到电容 - 电压转换器，并且响应用于在自电容感测模式下控制从电容式触摸矩阵提供给电容 - 电压转换器的信号的自发模式控制信号， 其中电容感测电路可配置为在互电容感测模式或自电容感测模式下操作。
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公开(公告)号：US11675024B2
公开(公告)日：2023-06-13
申请号：US17211149
申请日：2021-03-24
Applicant: STMicroelectronics S.r.l.
Inventor： Paolo Angelini , Roberto Pio Baorda , Danilo Karim Kaddouri
CPC classification number: G01R33/0017 , G01R33/07 , G01R33/075 , G01R15/202
Abstract: Hall sensing signals are received in a spinning readout pattern of subsequent readout phases, wherein the pattern is cyclically repeated at a spinning frequency and a polarity of the Hall sensor signals is reversed in two non-adjacent readout phases of the readout pattern. A signal storage circuit includes signal storage capacitors. An accumulation circuit includes accumulation capacitors. A switch network is selectively actuated to couple the signal storage capacitors with the accumulation capacitors synchronously with phases in the spinning readout pattern in subsequent alternating first and second periods. The spinning output is stored with alternating opposite signs on the signal storage capacitors and the Hall sensing signals are stored in the signal storage capacitors and then accumulated on the accumulation capacitors with alternate signs in subsequent periods. The accumulated output signal is then demodulated with a demodulation frequency half the spinning frequency.
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