公开(公告)号：US20230333583A1

公开(公告)日：2023-10-19

申请号：US18295774

申请日：2023-04-04

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Antonino CONTE ,  Marco RUTA ,  Francesco TOMAIUOLO ,  Michelangelo PISASALE ,  Marion Helne GRIMAL

IPC: G05F1/59 ,  G05F1/575

CPC classification number: G05F1/59 ,  G05F1/575

Abstract: A LDO regulator circuit comprises an input comparator and driver circuitry including transistors having a current flow path therethrough coupled to an output node of the regulator. First and second driver each comprises: driver transistors having the current flow paths therethrough coupled to the output node, capacitive boost circuitry that applies to the drive transistors a voltage-pumped replica of the comparison signal. Voltage refresh transistor circuitry coupled to the capacitive boost circuitry transfer thereon the voltage-pumped replica. The first and second drivers can be controllably switched between a first mode of operation, during which the current flow path through the driver transistors is conductive or non-conductive based on the voltage-pumped replica of the comparison signal, and a second mode, during which the voltage refresh transistor circuitry is activated to transfer the voltage-pumped replica of the comparison signal, and the current flow path through the driver transistors is non-conductive.

公开(公告)号：US20230336176A1

公开(公告)日：2023-10-19

申请号：US18296325

申请日：2023-04-05

Applicant: STMICROELECTRONICS S.r.l. ,  STMICROELECTRONICS (ALPS) SAS

Inventor： Antonino CONTE ,  Marco RUTA ,  Michelangelo PISASALE ,  Thomas JOUANNEAU

IPC: H03K19/0185 ,  H03K19/20

CPC classification number: H03K19/018521 ,  H03K19/20

Abstract: A level-shifter circuit receives one or more input signals in an input level domain and includes provides at an output node an output signal in an output level domain shifted with respect to the input level domain. The circuit includes output circuitry including a first drive node and a second drive node that receive first and second logical signals so that the output signal has a first output level or a second output level in the output level domain as a function of at least one of the first and second logical signals. The circuit includes first and second shift capacitors coupled to the first and second drive nodes as well as capacitor refresh circuitry.