公开(公告)号：US08681164B2

公开(公告)日：2014-03-25

申请号：US13655152

申请日：2012-10-18

Applicant: STMicroelectronics, Inc.

Inventor： Jefferson Eugene Owen ,  Raul Zegers Diaz ,  Osvaldo Colavin

IPC: G06F13/18 ,  G06F15/167

CPC classification number: G06T1/60 ,  G06F13/1605 ,  G06F13/18 ,  G06F15/167 ,  G09G5/001 ,  G09G5/363 ,  G09G2340/02 ,  G09G2360/18 ,  H04N19/423 ,  H04N19/427 ,  H04N19/61 ,  H04N21/443 ,  H04N21/4435

Abstract: An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory based on priority. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.

Abstract translation: 公开了电子系统，集成电路和显示方法。 电子系统包含第一设备，存储器以及诸如解码器/编码器的视频/音频压缩/解压缩设备。 电子系统被配置为允许第一设备和视频/音频压缩/解压缩设备共享存储器。 电子系统可以包括在计算机中，在这种情况下，存储器是主存储器。 存储器访问由一个或多个存储器接口实现，存储器直接耦合到总线，或者将第一设备和解码器/编码器直接耦合到总线。 仲裁器基于优先级选择性地提供对存储器的第一设备和/或解码器/编码器的访问。 仲裁器可以单片地集成到存储器接口中。 解码器可以是被配置为符合MPEG-2标准的视频解码器。 存储器可以存储从前一图像获得的预测图像。

公开(公告)号：US20140176587A1

公开(公告)日：2014-06-26

申请号：US14195414

申请日：2014-03-03

Applicant: STMicroelectronics, Inc

Inventor： Jefferson Eugene Owen ,  Raul Zegers Diaz ,  Osvaldo Colavin

IPC: G06T1/60 ,  G06F15/167 ,  G06F13/18

CPC classification number: G06T1/60 ,  G06F13/1605 ,  G06F13/18 ,  G06F15/167 ,  G09G5/001 ,  G09G5/363 ,  G09G2340/02 ,  G09G2360/18 ,  H04N19/423 ,  H04N19/427 ,  H04N19/61 ,  H04N21/443 ,  H04N21/4435

Abstract: An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory based on priority. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.

Abstract translation: 公开了电子系统，集成电路和显示方法。 电子系统包含第一设备，存储器以及诸如解码器/编码器的视频/音频压缩/解压缩设备。 电子系统被配置为允许第一设备和视频/音频压缩/解压缩设备共享存储器。 电子系统可以包括在计算机中，在这种情况下，存储器是主存储器。 存储器访问由一个或多个存储器接口实现，存储器直接耦合到总线，或者将第一设备和解码器/编码器直接耦合到总线。 仲裁器基于优先级选择性地提供对存储器的第一设备和/或解码器/编码器的访问。 仲裁器可以单片地集成到存储器接口中。 解码器可以是被配置为符合MPEG-2标准的视频解码器。 存储器可以存储从前一图像获得的预测图像。

公开(公告)号：US20130042072A1

公开(公告)日：2013-02-14

申请号：US13655152

申请日：2012-10-18

Applicant: STMicroelectronics, Inc.

Inventor： Jefferson Eugene Owen ,  Raul Zegers Diaz ,  Osvaldo Colavin

IPC: G06F12/08

CPC classification number: G06T1/60 ,  G06F13/1605 ,  G06F13/18 ,  G06F15/167 ,  G09G5/001 ,  G09G5/363 ,  G09G2340/02 ,  G09G2360/18 ,  H04N19/423 ,  H04N19/427 ,  H04N19/61 ,  H04N21/443 ,  H04N21/4435

Abstract: An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory based on priority. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.