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公开(公告)号：US12124385B2
公开(公告)日：2024-10-22
申请号：US17976395
申请日：2022-10-28
申请人： NXP B.V.
CPC分类号： G06F13/1626 , G06F13/161 , G06F13/18
摘要： Aspects of the disclosure are directed to allocating bandwidth. As may be implemented in accordance with one or more embodiments, respective amounts of bandwidth are allocated to respective application groups for each memory access cycle in a set of memory access cycles. Initial bonus bandwidth is provided to a first one of the application groups during one of the memory access cycles. The bonus bandwidth may include at least a portion of bandwidth allocated to and unused by one of the other respective application groups during the memory access cycle. Additional bonus bandwidth is selectively provided to the first application group during one of the memory access cycles based on the initial bonus bandwidth and a maximum amount of bonus bandwidth defined for the set of memory access cycles, in response to bandwidth allocated to one of the other respective application groups during the subsequent memory access cycle being unused.
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公开(公告)号：US20240320171A1
公开(公告)日：2024-09-26
申请号：US18731350
申请日：2024-06-03
申请人： SK hynix Inc.
发明人： Ji Wook KIM , Won Kyoo LEE , Ie Ryung PARK , Jeong Won SEO , A Hyun LEE
CPC分类号： G06F13/18 , G06F9/4818 , G06F13/1668
摘要： A data coding device may include a raw data storage configured to store raw data of which the total number of bits is 2N, a previous data storage configured to store previous data output before the raw data, a counter configured to count the number of reference data bits included in the raw data, and a data output circuit configured to invert and output the raw data according to a comparison result with the previous data when the number of reference data bits included in the raw data is N, and invert and output the raw data according to the number of reference data bits included in the raw data when the number of reference data bits included in the raw data is not N.
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公开(公告)号：US20240143519A1
公开(公告)日：2024-05-02
申请号：US17976395
申请日：2022-10-28
申请人： NXP B.V.
CPC分类号： G06F13/1626 , G06F9/5016 , G06F13/18
摘要： Aspects of the disclosure are directed to allocating bandwidth. As may be implemented in accordance with one or more embodiments, respective amounts of bandwidth are allocated to respective application groups for each memory access cycle in a set of memory access cycles. Initial bonus bandwidth is provided to a first one of the application groups during one of the memory access cycles. The bonus bandwidth may include at least a portion of bandwidth allocated to and unused by one of the other respective application groups during the memory access cycle. Additional bonus bandwidth is selectively provided to the first application group during one of the memory access cycles based on the initial bonus bandwidth and a maximum amount of bonus bandwidth defined for the set of memory access cycles, in response to bandwidth allocated to one of the other respective application groups during the subsequent memory access cycle being unused.
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公开(公告)号：US11915043B2
公开(公告)日：2024-02-27
申请号：US17162169
申请日：2021-01-29
申请人： Rubrik, Inc.
CPC分类号： G06F9/4881 , G06F13/18
摘要： In some examples, a data management and storage (DMS) system comprises peer DMS nodes in a node cluster, a distributed data store comprising local and cloud storage, and an IO request scheduler comprising at least one processor configured to perform operations in a method of scheduling IO requests. Example operations comprise implementing a kernel scheduler to schedule a flow of IO requests in the DMS system, and providing an adjustment layer to adjust the kernel scheduler based on an IO request prioritization. A flow of IO requests is identified and some examples implement an IO request prioritization based on the adjustments made by the adjustment layer.
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公开(公告)号：US11822789B2
公开(公告)日：2023-11-21
申请号：US17848221
申请日：2022-06-23
申请人： Intel Corporation
CPC分类号： G06F3/0608 , G06F3/0604 , G06F3/067 , G06F3/0611 , G06F3/0631 , G06F3/0638 , G06F3/0647 , G06F3/0653 , G06F3/0683 , G06F9/5016 , G06F12/02 , G06F12/023 , G06F13/18 , G06F2209/501 , G06F2209/5021 , G06F2212/1044
摘要： Methods, articles of manufacture, and apparatus are disclosed to manage workload memory allocation. An example method includes identifying a primary memory and a secondary memory associated with a platform, the secondary memory having first performance metrics different from second performance metrics of the primary memory, identifying access metrics associated with a plurality of data elements invoked by a workload during execution on the platform, prioritizing a list of the plurality of data elements based on the access metrics associated with corresponding ones of the plurality of data elements, and reallocating a first one of the plurality of data elements from the primary memory to the secondary memory based on the priority of the first one of the plurality of memory elements.
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6.发明公开公开(公告)号：US20230297519A1
公开(公告)日：2023-09-21
申请号：US17430323
申请日：2020-12-03
申请人： DEEPX CO., LTD.
发明人： Lok Won KIM
CPC分类号： G06F13/1668 , G06F13/18
摘要： An artificial neural network memory system includes at least one processor configured to generate a data access request corresponding to an artificial neural network operation; and at least one artificial neural network memory controller configured to sequentially record the data access request to generate an artificial neural network data locality pattern of the artificial neural network operation and generate an advance data access request which predicts a next data access request of the data access request generated by the at least one processor based on the artificial neural network data locality pattern.
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7.发明申请公开(公告)号：US20190114284A1
公开(公告)日：2019-04-18
申请号：US15783069
申请日：2017-10-13
IPC分类号： G06F13/42 , G06F13/40 , G06F12/0817 , G06F13/18
CPC分类号： G06F13/4239 , G06F12/0828 , G06F13/18 , G06F13/4059
摘要： Embodiments for a memory access broker system with application-controlled early write acknowledgment support. A memory access broker may be selectively enabled to facilitate early write acknowledgement (EWACK) operations and notification of failed EWACK write requests to one or more issuing applications such that the failed EWACK write requests are logged by the memory access broker for inspection by the one or more issuing applications.
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公开(公告)号：US20180329628A1
公开(公告)日：2018-11-15
申请号：US16042512
申请日：2018-07-23
CPC分类号： G06F3/061 , G06F3/0631 , G06F3/067 , G06F13/18
摘要： Examples of techniques for memory transaction prioritization for a memory are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method includes allocating, by a memory controller, a reserved portion of the memory controller to execute transactions. The method further includes receiving, by the memory controller, a priority based transaction from a processor to the memory. The method further includes determining, by the memory controller, whether to accommodate the priority based transaction based at least in part on a current processing state of the memory controller. The method further includes, based at least in part on determining to accommodate the priority based transaction, accommodating the priority based transaction by performing at least one of dropping a speculative command in a queue or using the reserved portion of the memory controller to execute the priority based transaction.
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9.发明申请公开(公告)号：US20180253381A1
公开(公告)日：2018-09-06
申请号：US15953782
申请日：2018-04-16
IPC分类号： G06F12/0842 , G06F13/16 , G06F13/18 , G06F13/14
CPC分类号： G06F12/0842 , G06F9/5083 , G06F12/0811 , G06F13/14 , G06F13/161 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F2212/1016 , G06F2212/502 , G06F2212/62
摘要： Disclosed aspects relate to cache management in a stream computing environment that uses a set of many-core hardware processors to process a stream of tuples by a plurality of processing elements which operate on the set of many-core hardware processors. The stream of tuples to be processed by the plurality of processing elements which operate on the set of many-core hardware processors may be received. A tuple-processing hardware-route on the set of many-core hardware processors may be determined based on a cache factor associated with the set of many-core hardware processors. The stream of tuples may be routed based on the tuple-processing hardware-route on the set of many-core hardware processors. The stream of tuples may be processed by the plurality of processing elements which operate on the set of many-core hardware processors.
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公开(公告)号：US20180203810A1
公开(公告)日：2018-07-19
申请号：US15918675
申请日：2018-03-12
申请人： Ampere Computing LLC
发明人： Kjeld Svendsen , Millind Mittal , Gaurav Singh
IPC分类号： G06F13/18
摘要： Proving for a framework for propagating priorities to a memory subsystem in a computing system environment is disclosed herein. By way of example, a memory access handler is provided for managing memory access requests and determining associated priorities. The memory access handler includes logic configured for propagating memory requests and the associated priorities to lower levels of a computer hierarchy. A memory subsystem receives the memory access requests and the priorities.
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