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公开(公告)号：US20240354043A1
公开(公告)日：2024-10-24
申请号：US18648737
申请日：2024-04-29
申请人： Intel Corporation
发明人： Eric J. Asperheim , Subramaniam Maiyuran , Kiran C. Veernapu , Sanjeev S. Jahagirdar , Balaji Vembu , Devan Burke , Philip R. Laws , Kamal Sinha , Abhishek R. Appu , Elmoustapha Ould-Ahmed-Vall , Peter L. Doyle , Joydeep Ray , Travis T. Schluessler , John H. Feit , Nikos Kaburlasos , Jacek Kwiatkowski , Altug Koker
IPC分类号： G06F3/14 , G06F3/01 , G06F3/0484 , G09G5/00 , G09G5/391
CPC分类号： G06F3/1438 , G06F3/013 , G06F3/0484 , G09G5/391 , G09G5/001 , G09G2340/0435 , G09G2352/00 , G09G2354/00 , G09G2360/08 , G09G2360/121
摘要： In accordance with some embodiments, the render rate is varied across and/or up and down the display screen. This may be done based on where the user is looking in order to reduce power consumption and/or increase performance. Specifically the screen display is separated into regions, such as quadrants. Each of these regions is rendered at a rate determined by at least one of what the user is currently looking at, what the user has looked at in the past and/or what it is predicted that the user will look at next. Areas of less focus may be rendered at a lower rate, reducing power consumption in some embodiments.
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2.发明授权公开(公告)号：US11887557B2
公开(公告)日：2024-01-30
申请号：US17624292
申请日：2020-07-03
发明人： Liang Wang , Yu Li , Jian Chen , Xingchun Ji , Yifang Guo
CPC分类号： G09G5/001 , G09G2320/0252 , G09G2330/021 , G09G2340/10 , G09G2354/00
摘要： Embodiments of this application relate to the field of image processing and display technologies, and provide a method for image processing based on vertical synchronization signals and an electronic device, to shorten a response latency of the electronic device and improve fluency (such as a touch latency) of the electronic device. A specific solution includes: drawing, by the electronic device, one or more first layers in response to a first vertical synchronization signal, and rendering the one or more first layers, and after rendering the one or more first layers, performing layer composing on the rendered one or more first layers to obtain a first image frame; and refreshing and displaying the first image frame in response to a second vertical synchronization signal.
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公开(公告)号：US11823642B2
公开(公告)日：2023-11-21
申请号：US17752651
申请日：2022-05-24
申请人： Apple Inc.
CPC分类号： G09G5/005 , G09G3/006 , G09G3/22 , G09G5/001 , G09G5/02 , G09G2320/046 , G09G2320/048 , G09G2320/0626 , G09G2320/0673 , G09G2330/10
摘要： An electronic display pipeline may process image data for display on an electronic display. The electronic display pipeline may include burn-in compensation statistics collection circuitry and burn-in compensation circuitry. The burn-in compensation statistics collection circuitry may collect image statistics based at least in part on the image data. The statistics may estimate a likely amount of non-uniform aging of the sub-pixels of the electronic display. The burn-in compensation circuitry may apply a gain to sub-pixels of the image data to account for non-uniform aging of corresponding sub-pixels of the electronic display. The applied gain may be based at least in part on the image statistics collected by the burn-in compensation statistics collection circuitry.
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公开(公告)号：US20230254517A1
公开(公告)日：2023-08-10
申请号：US18299448
申请日：2023-04-12
申请人： ROHM CO., LTD.
发明人： Hiroharu ENDO
IPC分类号： H04N19/93 , G09G5/377 , G09G5/00 , G09G5/36 , G09G5/02 , G09G3/20 , H04N19/44 , G09G5/12 , G09G5/18
CPC分类号： H04N19/93 , G09G3/20 , G09G3/2096 , G09G5/00 , G09G5/001 , G09G5/12 , G09G5/18 , G09G5/026 , G09G5/363 , G09G5/377 , H04N19/44 , G09G2340/02
摘要： A video input interface receives input video data in a normal state. A control input interface receives character data for On Screen Display (OSD) in a setup state. An encoder encodes the character data and stores encoded compressed data in a memory in the setup state. A decoder receives an instruction signal designating the character data to be displayed, reads, and decodes one piece of compressed data corresponding to the instruction signal from the memory, and reproduces the original character data in the normal state. A multiplexer superimposes character data on frame data and outputs the data.
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公开(公告)号：US11659211B2
公开(公告)日：2023-05-23
申请号：US17196521
申请日：2021-03-09
申请人： ROHM CO., LTD.
发明人： Hiroharu Endo
IPC分类号： H04N19/93 , G09G5/377 , G09G5/00 , G09G5/36 , G09G5/02 , G09G3/20 , H04N19/44 , G09G5/12 , G09G5/18
CPC分类号： H04N19/93 , G09G3/20 , G09G3/2096 , G09G5/00 , G09G5/001 , G09G5/026 , G09G5/12 , G09G5/18 , G09G5/363 , G09G5/377 , H04N19/44 , G09G2340/02
摘要： A video input interface receives input video data in a normal state. A control input interface receives character data for On Screen Display (OSD) in a setup state. An encoder encodes the character data and stores encoded compressed data in a memory in the setup state. A decoder receives an instruction signal designating the character data to be displayed, reads and decodes one piece of compressed data corresponding to the instruction signal from the memory, and reproduces the original character data in the normal state. A multiplexer superimposes character data on frame data and outputs the data.
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公开(公告)号：US11657781B2
公开(公告)日：2023-05-23
申请号：US17256558
申请日：2019-03-01
申请人： Intel Corporation
发明人： Anshuman Thakur , DongHo Hong , Karthik Veeramani , Arvind Tomar , Brent Insko , Atsuo Kuwahara , Zhengmin Li
CPC分类号： G09G5/12 , G02B27/017 , G06F3/1431 , G06T1/20 , G09G5/001 , G09G5/003 , G09G5/006 , A63F13/26 , A63F2300/8082 , G09G2360/18 , G09G2370/12 , G09G2370/16
摘要： Computers for supporting multiple virtual reality (VR) display devices and related methods are described herein. An example computer includes a graphics processing unit (GPU) to render frames for a first VR display device and a second VR display device, a memory to store frames rendered by the GPU for the first VR display device and the second VR display device, and a vertical synchronization (VSYNC) scheduler to transmit alternating first and second VSYNC signals to the GPU such that a time period between each of the first or second VSYNC signals and a subsequent one of the first or second VSYNC signals is substantially the same. The GPU is to, based on the first and second VSYNC signals, alternate between rendering a frame for the first VR display device and a frame for the second VR display device.
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公开(公告)号：US20230142472A1
公开(公告)日：2023-05-11
申请号：US17959374
申请日：2022-10-04
申请人： Intel Corporation
发明人： Eric J. Asperheim , Subramaniam Maiyuran , Kiran C. Veernapu , Sanjeev S. Jahagirdar , Balaji Vembu , Devan Burke , Philip R. Laws , Kamal Sinha , Abhishek R. Appu , Elmoustapha Ould-Ahmed-Vall , Peter L. Doyle , Joydeep Ray , Travis T. Schluessler , John H. Feit , Nikos Kaburlasos , Jacek Kwiatkowski , Altug Koker
IPC分类号： G06F3/14 , G06F3/01 , G09G5/391 , G06F3/0484
CPC分类号： G06F3/1438 , G06F3/013 , G09G5/391 , G06F3/0484 , G09G2354/00 , G09G2352/00 , G09G2360/08 , G09G2340/0435 , G09G2360/121 , G09G5/001
摘要： In accordance with some embodiments, the render rate is varied across and/or up and down the display screen. This may be done based on where the user is looking in order to reduce power consumption and/or increase performance. Specifically the screen display is separated into regions, such as quadrants. Each of these regions is rendered at a rate determined by at least one of what the user is currently looking at, what the user has looked at in the past and/or what it is predicted that the user will look at next. Areas of less focus may be rendered at a lower rate, reducing power consumption in some embodiments.
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8.发明申请公开(公告)号：US20190206371A1
公开(公告)日：2019-07-04
申请号：US15860296
申请日：2018-01-02
CPC分类号： G09G5/395 , G06F12/023 , G06F12/1027 , G06F2212/1044 , G06F2212/68 , G06T1/20 , G06T1/60 , G09G5/001 , G09G2360/12 , G09G2360/18
摘要： A device may allocate one or more frame buffers. In response to a command to open an application after allocating the one or more frame buffers, the device may reassign one or more of the frame buffers to the application. Furthermore, the device may store, based on instructions of the application, content data in the one or more reassigned frame buffers. The device may output, for display on a display screen, content based on the content data in the one or more reassigned frame buffers.
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公开(公告)号：US20180277054A1
公开(公告)日：2018-09-27
申请号：US15991860
申请日：2018-05-29
CPC分类号： G09G5/001 , G06F3/14 , G06F3/1423 , G06T1/60 , G09G5/395 , G09G2310/062 , G09G2310/08 , G09G2340/02 , G09G2340/0435 , G09G2350/00 , G09G2360/08 , G09G2360/12 , G09G2360/127 , G09G2370/022 , G09G2370/12 , H04N5/04 , H04N7/013
摘要： Systems and methods are configured to adjust the timing of source frame compression in response to fluctuations in a variable frame rate at which source frames are rendered into a buffer.
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公开(公告)号：US20180130441A1
公开(公告)日：2018-05-10
申请号：US15802926
申请日：2017-11-03
发明人： Jin-Young JEON
CPC分类号： G09G5/001 , G06F1/1613 , G06F1/3265 , G09G3/20 , G09G5/006 , G09G5/008 , G09G5/363 , G09G2310/0278 , G09G2310/08 , G09G2330/022 , G09G2360/127 , G09G2370/12 , G09G2370/16
摘要： An electronic device is provided. The electronic device includes a display, at least one processor, a memory that is electrically connected to the at least one processor, and a display driver integrated circuit that is electrically connected to the at least one processor. The at least one processor is configured to receive a synchronization signal request corresponding to a first process initiated by the at least one processor from the at least one processor, determine whether the first process is for displaying an image in response to the synchronization signal request, and control an activation state of the display driver integrated circuit for displaying the image based on a determination result. The memory is configured to store instructions for the at least one processor to initiate and run the first process.
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