公开(公告)号：US20040150443A1

公开(公告)日：2004-08-05

申请号：US10761760

申请日：2004-01-21

Applicant: STMicroelectronics, Inc.

Inventor： Srikanth R. Muroor

IPC: H03L007/06

CPC classification number: H03L7/099 ,  H03K3/0231

Abstract: There is disclosed a voltage controlled oscillator (VCO) that receives nullV(IN) and nullV(IN) control voltages and outputs a VCO output signal having an oscillation frequency determined by the nullV(IN) and nullV(IN) control voltages. The VCO comprises: 1) a storage capacitor charged linearly by a constant charge current and discharged linearly by a constant discharge current; 2) a comparator for comparing the storage capacitor voltage to an upper threshold voltage and a lower threshold voltage. The comparator output drops to a negative saturation voltage (nullV(SAT)) when the storage capacitor voltage rises above the upper threshold voltage and rises to a positive saturation voltage (nullV(SAT)) when the storage capacitor voltage drops below the lower threshold voltage. The VCO also comprises: 3) a constant charge current source for injecting the constant charge current into the storage capacitor when the comparator output rises to the positive saturation voltage; and 4) a constant discharge current source for draining the constant discharge current from the storage capacitor when the comparator output drops to the negative saturation voltage.

Abstract translation: 公开了一种压控振荡器（VCO），其接收+ V（IN）和-V（IN）控制电压，并且输出具有由+ V（IN）和-V（IN）控制确定的振荡频率的VCO输出信号 电压。 该VCO包括：1）通过恒定充电电流线性地充电并通过恒定放电电流线性放电的存储电容器; 2）用于将存储电容器电压与上阈值电压和较低阈值电压进行比较的比较器。 当存储电容器电压下降到低于下限值时，当存储电容器电压上升到高于阈值电压并上升到正饱和电压（+ V（SAT））时，比较器输出下降到负饱和电压（-V（SAT）） 阈值电压。 VCO还包括：3）恒定的充电电流源，用于当比较器输出上升到正饱和电压时，将恒定的充电电流注入到存储电容器中; 以及4）恒定放电电流源，用于当比较器输出下降到负饱和电压时从存储电容器排出恒定的放电电流。

公开(公告)号：US20030145152A1

公开(公告)日：2003-07-31

申请号：US10060739

申请日：2002-01-30

Applicant: STMicroelectronics, Inc.

Inventor： Srikanth R. Muroor

IPC: H03L007/00

CPC classification number: H03L7/099 ,  H03K3/0231

Abstract: There is disclosed a voltage controlled oscillator (VCO) that receives nullV(IN) and nullV(IN) control voltages and outputs a VCO output signal having an oscillation frequency determined by the nullV(IN) and nullV(IN) control voltages. The VCO comprises: 1) a storage capacitor charged linearly by a constant charge current and too discharged linearly by a constant discharge current; 2) a comparator for comparing the storage capacitor voltage to an upper threshold voltage and a lower threshold voltage. The comparator output drops to a negative saturation voltage (nullV(SAT)) when the storage capacitor voltage rises above the upper threshold voltage and rises to a positive saturation voltage (nullV(SAT)) when the storage capacitor voltage drops below the lower threshold voltage. The VCO also comprises: 3) a constant charge current source for injecting the constant charge current into the storage capacitor when the comparator output rises to the positive saturation voltage; and 4) a constant discharge current source for draining the constant discharge current from the storage capacitor when the comparator output drops to the negative saturation voltage.

Abstract translation: 公开了一种压控振荡器（VCO），其接收+ V（IN）和-V（IN）控制电压，并且输出具有由+ V（IN）和-V（IN）控制确定的振荡频率的VCO输出信号 电压。 VCO包括：1）通过恒定充电电流线性地充电并且由恒定的放电电流线性地放电的存储电容器; 2）用于将存储电容器电压与上阈值电压和较低阈值电压进行比较的比较器。 当存储电容器电压下降到低于下限值时，当存储电容器电压上升到高于阈值电压并上升到正饱和电压（+ V（SAT））时，比较器输出下降到负饱和电压（-V（SAT）） 阈值电压。 VCO还包括：3）恒定的充电电流源，用于当比较器输出上升到正饱和电压时，将恒定的充电电流注入到存储电容器中; 以及4）恒定放电电流源，用于当比较器输出下降到负饱和电压时从存储电容器排出恒定的放电电流。

公开(公告)号：US20030145145A1

公开(公告)日：2003-07-31

申请号：US10060454

申请日：2002-01-30

Applicant: STMicroelectronics, Inc.

Inventor： Srikanth R. Muroor

IPC: G06F013/14

CPC classification number: G06F13/4072 ,  G06F13/364 ,  Y02D10/14 ,  Y02D10/151

Abstract: A bus arbitrator for use in a shared bus system in which N bus devices request access to a shared bus. The bus arbitrator slowly activates and rapidly de-activates tristate line drivers coupled to the shared bus. The bus arbitrator comprises: 1) an input interface for receiving a first bus access request signal from a first bus device; 2) a delay circuit that receives the first bus access request signal from the input interface and generates a time-delayed first bus access request signal; and 3) a comparator circuit that receives the first bus access request signal from the input interface and the time-delayed first bus access request signal from the delay circuit and generates a line driver enable signal only if both of the first bus access request signal and the time-delayed first bus access request signal are enabled. The comparator circuit disables the line driver enable signal if either of the first bus access request signal or the time-delayed first bus access request signal is disabled.

Abstract translation: 一种用于共用总线系统中的总线仲裁器，其中N总线设备请求访问共享总线。 总线仲裁器缓慢激活并快速停用耦合到共享总线的三态线路驱动器。 总线仲裁器包括：1）用于从第一总线设备接收第一总线访问请求信号的输入接口; 2）延迟电路，其从所述输入接口接收所述第一总线访问请求信号，并产生时间延迟的第一总线访问请求信号; 以及3）比较器电路，其从所述输入接口接收所述第一总线访问请求信号，并且从所述延迟电路接收所述时间延迟的第一总线访问请求信号，并且仅在所述第一总线访问请求信号和 时间延迟的第一总线访问请求信号被使能。 如果第一总线访问请求信号或时间延迟的第一总线访问请求信号中的任一个被禁用，则比较器电路禁用线路驱动器使能信号。

公开(公告)号：US20030145244A1

公开(公告)日：2003-07-31

申请号：US10062620

申请日：2002-01-31

Applicant: STMicroelectronics, Inc.

Inventor： Srikanth R. Muroor

IPC: G06F001/04

CPC classification number: G06F1/08

Abstract: A clock selection circuit for selecting between two clock sources. The clock selection circuit has two independent clock inputs, CLK1 and CLK2, where no assumptions are made regarding frequency or phase relationship between the two clocks inputs. Two asynchronous inputs, START1 and START2 (both active high), are used to start and stop the clocks. As long as one clock is active, the START signal of the other clock will not have any effect. The invention includes interlock circuitry that ensures that at any given time only one clock is enabled to the output. Disabling the corresponding START signal disables the clock signal.

Abstract translation: 用于在两个时钟源之间进行选择的时钟选择电路。 时钟选择电路有两个独立的时钟输入CLK1和CLK2，在这两个时钟输入之间没有关于频率或相位关系的假设。 两个异步输入START1和START2（均为高电平有效）用于启动和停止时钟。 只要一个时钟有效，另一个时钟的START信号就不会有任何影响。 本发明包括互锁电路，其确保在任何给定时间仅对输出启用一个时钟。 禁用相应的START信号禁止时钟信号。