公开(公告)号：US20240345987A1

公开(公告)日：2024-10-17

申请号：US18756821

申请日：2024-06-27

申请人： STMicroelectronics S.r.l.

发明人： Daniele Oreggia ,  Alessandro Cannone ,  Diego Alagna ,  Marcello Raimondi

IPC分类号： G06F13/42 ,  G06F13/364 ,  G06F13/40

CPC分类号： G06F13/4291 ,  G06F13/364 ,  G06F13/4022

摘要： A battery management system includes: a controller; a master battery management integrated circuit (BMIC) device coupled to the controller and configured to communicate with the controller through a standard Serial Peripheral Interface (SPI) protocol; and a first slave BMIC device and a second slave BMIC device that are connected in a daisy chain configuration and communicating through Isolated SPI interfaces, where the first slave BMIC device is coupled to the master BMIC through an Isolated SPI interface, where the Isolated SPI interface uses a differential signal comprising a positive signal and a complementary negative signal, where a bit frame of the positive signal includes a bit period followed by an idle period having a same duration as the bit period, where the first slave BMIC device and the second slave BMIC device are configured to be coupled to a first battery pack and a second battery pack, respectively.

公开(公告)号：US12026112B2

公开(公告)日：2024-07-02

申请号：US17943183

申请日：2022-09-12

申请人： AyDeeKay LLC

发明人： Scott David Kee

IPC分类号： G06F13/36 ,  G06F3/06 ,  G06F12/06 ,  G06F12/0866 ,  G06F13/14 ,  G06F13/16 ,  G06F13/26 ,  G06F13/28 ,  G06F13/364 ,  G06F13/40 ,  G06F13/42 ,  G06F21/76

CPC分类号： G06F13/26 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0638 ,  G06F12/0866 ,  G06F13/14 ,  G06F13/1668 ,  G06F13/1684 ,  G06F13/28 ,  G06F13/364 ,  G06F13/4027 ,  G06F13/4068 ,  G06F13/4282 ,  G06F21/76 ,  G06F2213/0062 ,  G06F2213/40 ,  G06F2221/2103

摘要： Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.

公开(公告)号：US11995012B2

公开(公告)日：2024-05-28

申请号：US17695204

申请日：2022-03-15

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Avi Klein ,  Dror Barash ,  Guy Horowitz ,  Oren Reinherz ,  Roi Herman ,  Amit Eisenberg

IPC分类号： G06F13/24 ,  G02B27/01 ,  G06F13/364 ,  G06F13/42 ,  H04N13/243 ,  H04N13/296

CPC分类号： G06F13/24 ,  G02B27/017 ,  G06F13/364 ,  G06F13/4256 ,  G06F13/4291 ,  H04N13/243 ,  H04N13/296 ,  G02B2027/0178

摘要： A multi-image sensor system includes data, clock, and control buses, an application processor connected to the data bus and the clock bus, and image sensors connected in a daisy chain using the control bus. A first one of the image sensors configured as a master outputs image data to the data bus, outputs a first clock signal to the clock bus, and sends a control signal to a second one of the image sensors in the daisy chain through the control bus. The control signal has a first logic state when output of the first image data starts and a second other logic state when output of the first image data ends. The second image sensor connects itself to the data bus and the master disconnects itself from the data bus according to a state of the first control signal.

公开(公告)号：US20240086354A1

公开(公告)日：2024-03-14

申请号：US18515091

申请日：2023-11-20

申请人： Samsung Electronics Co., Ltd.

发明人： DongSik CHO ,  Jeonghoon KIM ,  Rohitaswa BHATTACHARYA ,  Jaeshin LEE ,  Honggi JEONG

IPC分类号： G06F13/40 ,  G06F13/364

CPC分类号： G06F13/4004 ,  G06F13/364 ,  Y02D10/00

摘要： A system on chip, semiconductor device, and/or method are provided that include a plurality of masters, an interface, and a semaphore unit. The interface interfaces the plurality of masters with a slave device. The semaphore unit detects requests of the plurality of masters, controlling the salve device, about an access to the interface and assigns a semaphore about each of the plurality of masters by a specific operation unit according to the detection result.

公开(公告)号：US11886367B2

公开(公告)日：2024-01-30

申请号：US17545930

申请日：2021-12-08

申请人： ATI Technologies ULC

发明人： Michael E. McLean ,  Philip Ng

IPC分类号： G06F13/372 ,  G06F13/364 ,  G06F9/48 ,  G06F13/40 ,  G06F13/366

CPC分类号： G06F13/372 ,  G06F9/4812 ,  G06F13/364 ,  G06F13/366 ,  G06F13/4059

摘要： An arbitration system receives requests to access a destination during an arbitration window that spans multiple processor clock cycles. During each clock cycle, the destination is monitored to determine whether the destination is suffering from backpressure by receiving more requests than the destination is able to accommodate during the clock cycle. In response to detecting backpressure, a masking index value assigned to a requesting source is incremented, which limits an amount of requests from the source that will be granted destination access during a subsequent arbitration window. Alternatively, in response to detecting an absence of backpressure during an arbitration window, the masking index value is decremented, which increases the amount of requests from the source that will be granted destination access during a subsequent arbitration window. This arbitration process continues for successive arbitration windows, oscillating between incrementing and decrementing the masking index value during the successive arbitration windows.

公开(公告)号：US20230273894A1

公开(公告)日：2023-08-31

申请号：US17682447

申请日：2022-02-28

申请人： NXP USA, Inc.

发明人： Nicholas Justin Mountford Spence

IPC分类号： G06F13/42 ,  G06F13/364 ,  G06F13/40

CPC分类号： G06F13/4282 ,  G06F13/364 ,  G06F13/4022

摘要： Digitally controllable elements capable of influencing operation of a power amplifier module are coupled to an interface gateway device using a first serial data interface that communicates using a first serial protocol. The interface gateway device receives serial data on multiple external serial data interfaces that utilize various serial protocols, and converts the various serial protocols to the first serial protocol. Each digitally controllable element includes address control logic that decodes an address presented on the first serial data interface as well as a device specific ID. In response to the decoding, physical registers in different digitally controllable elements are written.

公开(公告)号：US20230244611A1

公开(公告)日：2023-08-03

申请号：US18083703

申请日：2022-12-19

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Abhijeet Ashok Chachad ,  Raguram Damodaran ,  Ramakrishnan Venkatasubramanian ,  Joseph Raymond Michael Zbiciak

IPC分类号： G06F12/1081 ,  G06F7/483 ,  G06F9/30 ,  H03M13/35 ,  H03M13/29 ,  G06F11/10 ,  G06F13/16 ,  G06F13/18 ,  H03K19/00 ,  G06F1/3296 ,  H03K21/00 ,  G06F12/02 ,  G06F12/12 ,  G06F12/0811 ,  G06F12/0815

CPC分类号： G06F12/1081 ,  G06F7/483 ,  G06F9/3012 ,  H03M13/353 ,  H03M13/2903 ,  G06F11/1064 ,  G06F13/1605 ,  G06F13/18 ,  H03K19/0016 ,  G06F1/3296 ,  H03K21/00 ,  G06F12/0246 ,  G06F12/12 ,  G06F12/0811 ,  G06F12/0815 ,  G06F13/1652 ,  G06F13/1657 ,  G06F13/1663 ,  G06F13/364

摘要： A queuing requester for access to a memory system is provided. Transaction requests are received from two or more requestors for access to the memory system. Each transaction request includes an associated priority value. A request queue of the received transaction requests is formed in the queuing requester. Each transaction request includes an associated priority value. A highest priority value of all pending transaction requests within the request queue is determined. An elevated priority value is selected when the highest priority value is higher than the priority value of an oldest transaction request in the request queue; otherwise the priority value of the oldest transaction request is selected. The oldest transaction request in the request queue with the selected priority value is then provided to the memory system. An arbitration contest with other requesters for access to the memory system is performed using the selected priority value.

公开(公告)号：US20230205717A1

公开(公告)日：2023-06-29

申请号：US18179052

申请日：2023-03-06

申请人： Samsung Electronics Co., Ltd.

发明人： DongSik CHO ,  Jeonghoon Kim ,  Rohitaswa Bhattacharya ,  Jaeshin Lee ,  Honggi Jeong

IPC分类号： G06F13/40 ,  G06F13/364

CPC分类号： G06F13/4004 ,  G06F13/364 ,  Y02D10/00

摘要： A system on chip, semiconductor device, and/or method are provided that include a plurality of masters, an interface, and a semaphore unit. The interface interfaces the plurality of masters with a slave device. The semaphore unit detects requests of the plurality of masters, controlling the salve device, about an access to the interface and assigns a semaphore about each of the plurality of masters by a specific operation unit according to the detection result.

公开(公告)号：US11681642B2

公开(公告)日：2023-06-20

申请号：US17328143

申请日：2021-05-24

申请人： Graphcore Limited

发明人： Graham Bernard Cunningham ,  Daniel John Pelham Wilkinson

IPC分类号： G06F13/374 ,  G06F13/364 ,  G06F15/173

CPC分类号： G06F13/374 ,  G06F13/364 ,  G06F15/17375

摘要： A device comprising: a control bus; a plurality of requesting circuits each accessible on the control bus, wherein each of the plurality of requesting circuits is operable to dispatch read or write requests to the control bus for delivery to at least one of a plurality of receiving circuits, and the plurality of receiving circuits each accessible on the control bus, and each of which is operable to receive requests from the at least one control bus and service the requests by providing at least one of read or write access to storage associated with the respective receiving circuit, wherein the control bus provides a ring path configured to support, the requests in circulation in the ring path, wherein the control bus is configured to propagate each of at least some of the requests at least until those requests have been serviced by at least one of the receiving circuits.

公开(公告)号：US20190155781A1

公开(公告)日：2019-05-23

申请号：US15819641

申请日：2017-11-21

申请人： QUALCOMM Incorporated

发明人： Lior Amarilio ,  Yuval Corey Hershko ,  Nir Strauss

IPC分类号： G06F13/42 ,  G06F13/364 ,  G06F15/78

CPC分类号： G06F13/4291 ,  G06F1/3287 ,  G06F13/362 ,  G06F13/364 ,  G06F15/7807

摘要： Systems and methods to transfer master duties to a slave on a communication bus are disclosed. A master of a communication bus determines that one or more slaves are capable of serving as a sub-master, including providing a clock signal and owning control information bits. Once that determination is made, the master may determine that processing within the master is not required for a particular activity on the bus. The master then alerts one such capable slave to prepare to assume sub-master duties. Once the slave confirms that the slave is ready to assume the sub-master duties, the master may transmit a handover frame on the bus, and the slave begins acting as a sub-master. The master may then enter a low-power state, which may promote power savings, reduce heat generation, and provide other advantages.