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    Test circuit to debug missed test clock pulses
    1.
    发明授权
    Test circuit to debug missed test clock pulses 有权

    公开(公告)号：US10302700B2

    公开(公告)日：2019-05-28

    申请号：US15473100

    申请日：2017-03-29

    Applicant: STMicroelectronics, Inc.

    Inventor： Vinay Kumar ,  Pramod Kumar

    IPC: G01R31/28 ,  G01R31/3185 ,  G06F11/25 ,  G01R31/317 ,  G01R31/3181 ,  G01R31/3183

    Abstract: Disclosed herein is a test circuit for a device under test. The test circuit includes a test data source and a test data target. A debug chain is coupled between the test data source and test data target, and operates in either a clock debug mode or a test mode. The debug chain, when in the test mode, is deactivated. The debug chain, when in the clock debug mode, receives the test pattern data from the test data source and stores the test pattern data, generates a clock debug signature from the stored test pattern data while clocked by a test clock, and outputs the clock debug signature to the test data target, the clock debug signature indicative of whether the test clock is operating properly.

    Test circuit capable of measuring PLL clock signal in ATPG mode
    3.
    发明授权
    Test circuit capable of measuring PLL clock signal in ATPG mode 有权

    公开(公告)号：US10261128B2

    公开(公告)日：2019-04-16

    申请号：US15466001

    申请日：2017-03-22

    Applicant: STMicroelectronics, Inc.

    Inventor： Pramod Kumar ,  Vinay Kumar

    IPC: G01R31/317 ,  G01R31/3177

    Abstract: Disclosed herein is a test circuit for a device under test. The test circuit includes a scan chain configured to receive test pattern data and to shift the test pattern data to the device under test, and being clocked by a reference clock, and a clock circuit configured to operate in either a clock generation mode or a frequency determination mode. The clock circuit, when in the clock generation mode and when the test circuit is in a normal mode of operation, is configured to pass a first clock signal to the device under test. The clock circuit, when in the clock generation mode and when the test circuit is in a test mode of operation, is configured to pass the reference clock to the device under test. The clock circuit, when in the frequency determination mode, counts a frequency of the first clock signal.

    TEST CIRCUIT CAPABLE OF MEASURING PLL CLOCK SIGNAL IN ATPG MODE
    4.
    发明申请
    TEST CIRCUIT CAPABLE OF MEASURING PLL CLOCK SIGNAL IN ATPG MODE 审中-公开

    公开(公告)号：US20180275197A1

    公开(公告)日：2018-09-27

    申请号：US15466001

    申请日：2017-03-22

    Applicant: STMicroelectronics, Inc.

    Inventor： Pramod Kumar ,  Vinay Kumar

    IPC: G01R31/317 ,  G01R31/3177

    CPC classification number: G01R31/31727 ,  G01R31/31701 ,  G01R31/31723 ,  G01R31/31725 ,  G01R31/3177

    Abstract: Disclosed herein is a test circuit for a device under test. The test circuit includes a scan chain configured to receive test pattern data and to shift the test pattern data to the device under test, and being clocked by a reference clock, and a clock circuit configured to operate in either a clock generation mode or a frequency determination mode. The clock circuit, when in the clock generation mode and when the test circuit is in a normal mode of operation, is configured to pass a first clock signal to the device under test. The clock circuit, when in the clock generation mode and when the test circuit is in a test mode of operation, is configured to pass the reference clock to the device under test. The clock circuit, when in the frequency determination mode, counts a frequency of the first clock signal.

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