公开(公告)号：US20220317719A1

公开(公告)日：2022-10-06

申请号：US17707321

申请日：2022-03-29

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Alps) SAS

Inventor： Vratislav MICHAL ,  Regis ROUSSET

IPC: G05F3/30

Abstract: A band-gap circuit for generating a bandgap reference signal includes a first bipolar transistor and a second bipolar transistor of a same type among PNP and NPN types. The first and second bipolar transistors are configured to generate a current varying proportionally with the temperature. A capacitor is connected between a base and an emitter of one or both of the first and second bipolar transistors.

公开(公告)号：US20240243712A1

公开(公告)日：2024-07-18

申请号：US18411748

申请日：2024-01-12

Applicant: STMicroelectronics (Alps) SAS

Inventor： Vratislav MICHAL ,  Samuel FOULON

IPC: H03F3/45 ,  H03F1/32

CPC classification number: H03F3/45183 ,  H03F1/3205 ,  H03F3/45744

Abstract: A differential pair circuit includes a first branch and a second branch having a common first node. Each of the first and second branches includes at least one transistor having a conduction node directly connected to the common first node. A third branch couples the common first node to a power supply node. The third branch includes a current source in series with a resistive element.

公开(公告)号：US20150262776A1

公开(公告)日：2015-09-17

申请号：US14657991

申请日：2015-03-13

Applicant: STMicroelectronics (Alps) SAS

Inventor： Vratislav MICHAL ,  Denis COTTIN

IPC: H01H47/00

CPC classification number: H01H47/00 ,  H03K17/167 ,  H03K17/30 ,  H03K2017/307 ,  Y10T307/76

Abstract: A circuit including: a plurality of first switches connected in parallel between a first terminal and a second terminal; and a control circuit capable of implementing the following steps at each period of a clock signal: comparing the voltage between the first and second terminals with a reference voltage; if the voltage between the first and second terminals is greater than the reference voltage, turning on one of the first switches without modifying the state of the other switches; and if the voltage between the first and second terminals is smaller than the reference voltage, turning off one of the first switches without modifying the state of the other switches.

Abstract translation: 一种电路，包括：在第一端子和第二端子之间并联连接的多个第一开关; 以及控制电路，其能够在时钟信号的每个周期执行以下步骤：将所述第一和第二端子之间的电压与参考电压进行比较; 如果第一和第二端子之间的电压大于参考电压，则在不改变其它开关的状态的情况下，接通第一开关中的一个开关; 并且如果第一和第二端子之间的电压小于参考电压，则在不修改其他开关的状态的情况下关闭其中一个开关。

公开(公告)号：US20170179816A1

公开(公告)日：2017-06-22

申请号：US14975138

申请日：2015-12-18

Applicant: STMicroelectronics (Alps) SAS

Inventor： Vratislav MICHAL

IPC: H02M3/04

CPC classification number: H02M3/04 ,  H02M3/156 ,  H02M3/1588 ,  H02M2001/0054 ,  Y02B70/1466 ,  Y02B70/1491

Abstract: A method and apparatus for detecting a critical duty cycle that maximizes an output power of a boost converter is provided. In the method and apparatus, boost converter is operated may be operated at or below the critical duty cycle. In the method and apparatus, a first voltage that is a function of an output voltage of a boost converter and voltage drops across a first set of parasitic resistances of the boost converter is detected. A second voltage that is a function voltage drops across a second set of parasitic resistances of the boost converter is also detected. The voltages are compared to determine the critical duty cycle and the boost converter is operated in accordance with a duty cycle that does not exceed the critical duty cycle.

公开(公告)号：US20230239057A1

公开(公告)日：2023-07-27

申请号：US18150115

申请日：2023-01-04

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS ,  STMICROELECTRONICS (ALPS) SAS

Inventor： Nicolas MOENECLAEY ,  Vratislav MICHAL ,  Jean-Luc PATRY

IPC: H04B10/61

CPC classification number: H04B10/616

Abstract: The present disclosure is directed to a light-signal communication receiver device including a photo-receiving diode configured to generate a current signal on a first node from a received light signal, a preamplifier configured to convert the current signal on the first node into a voltage signal on a second node, and a differential amplifier including a first input connected to the first node and a second input connected to a third node coupled to the second node via an adjustment circuit. The adjustment circuit is configured to offset the level of the voltage signal of the second node, on the third node, in a controlled manner by a control signal.