公开(公告)号：US20190296007A1

公开(公告)日：2019-09-26

申请号：US16436289

申请日：2019-06-10

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Jean JIMENEZ

IPC: H01L27/06 ,  H01L29/732 ,  H01L29/808 ,  H01L29/66 ,  H01L21/8228 ,  H01L27/092 ,  H01L21/8238 ,  H01L27/082 ,  H01L21/8249

Abstract: An integrated circuit of the BiCMOS type includes at least one vertical junction field-effect transistor. The vertical junction field-effect transistor is formed to include a channel region having a critical dimension of active surface that is controlled by photolithography. A gate region of the transistor is formed by two spaced apart first trenches in that are filled with a doped semiconductor material, wherein the two spaced apart first trenches bound the channel region and set the critical dimension.

公开(公告)号：US20180374983A1

公开(公告)日：2018-12-27

申请号：US16008613

申请日：2018-06-14

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Dominique GOLANSKI ,  Jean JIMENEZ ,  Didier DUTARTRE ,  Olivier GONNARD

IPC: H01L31/18 ,  H01L31/107 ,  H01L29/66 ,  H01L21/265

Abstract: A method for manufacturing a SPAD photodiode starts with the delimitation of a formation area for the SPAD photodiode in a layer of semiconductor material that is doped with a first dopant type. Dopant of a second dopant type is implanted in the layer of semiconductor material to form a buried region within the formation area. An epitaxial layer is then grown on the layer of semiconductor material at least over the formation area. MOS transistors are then formed on and in the epitaxial layer at locations outside of the formation area.