公开(公告)号：US11650738B2

公开(公告)日：2023-05-16

申请号：US17111778

申请日：2020-12-04

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Gerald Briat ,  Stephane Marmey

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0652 ,  G06F3/0659 ,  G06F3/0679

Abstract: The integrity of a memory is checked by: storing data representative of an operation to be executed in the memory; executing the operation; and erasing the data once the execution is complete.

公开(公告)号：US11106582B2

公开(公告)日：2021-08-31

申请号：US16530049

申请日：2019-08-02

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Gerald Briat

IPC: G06F12/0806

Abstract: A device includes first and second buffers fillable with contents of memory locations. A selection circuit is configured to select a filling mode between simultaneous filling of the buffers and sequential filling of the buffers. In some examples, the device can be a system on a chip that includes a non-volatile memory and a processor.

公开(公告)号：US20210011727A1

公开(公告)日：2021-01-14

申请号：US16922095

申请日：2020-07-07

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Michael Giovannini ,  Gerald Briat

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/448

Abstract: In an embodiment a method for operating an integrated circuit includes sequentially requesting, by a processor of an integrated circuit, different instruction lines; determining, by a first comparator of the integrated circuit, while the processor processes a current instruction line supplied in response to a corresponding request, whether or not at least one of the instructions of the current instruction line is a branch instruction by comparing the at least one of the instructions to reference instructions; executing, by the processor, all instructions of the current instruction line before executing a next instruction line when the at least one instruction is a branch instruction from a program memory of the integrated circuit; and executing, by the processor, all instruction of the current instruction line before executing a next instruction line from first and second volatile memory of the integrated circuit when the at least one instruction is not a branch instruction.

公开(公告)号：US11567558B2

公开(公告)日：2023-01-31

申请号：US17111877

申请日：2020-12-04

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Gerald Briat

IPC: G06F1/3234 ,  G06F3/06 ,  G11C16/30

Abstract: A memory chip includes at least two memory blocks. In a method for controlling power supply for the memory blocks of the memory chip, each memory block receives a command for switching to standby mode. The commands are issued, for example by a processor, separately for each memory block in order to be able to individually place the memory block in standby mode.

公开(公告)号：US20200057719A1

公开(公告)日：2020-02-20

申请号：US16530049

申请日：2019-08-02

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Gerald Briat

IPC: G06F12/0806

Abstract: A device includes first and second buffers fillable with contents of memory locations. A selection circuit is configured to select a filling mode between simultaneous filling of the buffers and sequential filling of the buffers. In some examples, the device can be a system on a chip that includes a non-volatile memory and a processor.