公开(公告)号：US20210011727A1

公开(公告)日：2021-01-14

申请号：US16922095

申请日：2020-07-07

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Michael Giovannini ,  Gerald Briat

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/448

Abstract: In an embodiment a method for operating an integrated circuit includes sequentially requesting, by a processor of an integrated circuit, different instruction lines; determining, by a first comparator of the integrated circuit, while the processor processes a current instruction line supplied in response to a corresponding request, whether or not at least one of the instructions of the current instruction line is a branch instruction by comparing the at least one of the instructions to reference instructions; executing, by the processor, all instructions of the current instruction line before executing a next instruction line when the at least one instruction is a branch instruction from a program memory of the integrated circuit; and executing, by the processor, all instruction of the current instruction line before executing a next instruction line from first and second volatile memory of the integrated circuit when the at least one instruction is not a branch instruction.

公开(公告)号：US20200371546A1

公开(公告)日：2020-11-26

申请号：US16879126

申请日：2020-05-20

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Michael Giovannini

IPC: G06F1/08 ,  H03L7/097

Abstract: A method for modifying the frequency of a clock signal clocking an integrated circuit supplied by a voltage controller, comprises, in response to a command for the modification, varying the frequency of the clock signal at a rate allowing a supply voltage to be controlled by the controller. The variation comprises at least one series of successive divisions of the frequency of the clock signal into successive intermediate signals of respective intermediate frequencies.

公开(公告)号：US11442530B2

公开(公告)日：2022-09-13

申请号：US17109452

申请日：2020-12-02

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Michael Giovannini

IPC: G06F1/32 ,  G11C5/14 ,  G06F1/3234 ,  G06F1/3225 ,  G06F1/3287

Abstract: A memory includes writable memory units. Each memory unit is configurable: in a retention state wherein the memory unit is capable of retaining data until a subsequent power-off of the memory unit, and in a non-retention state wherein the memory unit does not retain data and consumes less power than in the first state. A controller configures any memory unit of the memory having undergone at least one write access since its last power-up to be in the retention state. The controller further configures at least one memory unit of the memory that has not undergone any write access since its last power-up in the non-retention state.

公开(公告)号：US11487314B2

公开(公告)日：2022-11-01

申请号：US17412816

申请日：2021-08-26

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Michael Giovannini

IPC: G06F1/08 ,  H03L7/097

Abstract: An embodiment method for modifying the frequency of a clock signal clocking an integrated circuit supplied by a voltage controller comprises, in response to a command for the modification, varying the frequency of the clock signal at a rate allowing a supply voltage to be controlled by the controller. The variation comprises at least one series of successive divisions of the frequency of the clock signal into successive intermediate signals of respective intermediate frequencies.

公开(公告)号：US20210389792A1

公开(公告)日：2021-12-16

申请号：US17412816

申请日：2021-08-26

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Michael Giovannini

IPC: G06F1/08 ,  H03L7/097

Abstract: An embodiment method for modifying the frequency of a clock signal clocking an integrated circuit supplied by a voltage controller comprises, in response to a command for the modification, varying the frequency of the clock signal at a rate allowing a supply voltage to be controlled by the controller. The variation comprises at least one series of successive divisions of the frequency of the clock signal into successive intermediate signals of respective intermediate frequencies.

公开(公告)号：US11132016B2

公开(公告)日：2021-09-28

申请号：US16879126

申请日：2020-05-20

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Michael Giovannini

IPC: G06F1/08 ,  H03L7/097

Abstract: A method for modifying the frequency of a clock signal clocking an integrated circuit supplied by a voltage controller, comprises, in response to a command for the modification, varying the frequency of the clock signal at a rate allowing a supply voltage to be controlled by the controller. The variation comprises at least one series of successive divisions of the frequency of the clock signal into successive intermediate signals of respective intermediate frequencies.