公开(公告)号：US10998378B2

公开(公告)日：2021-05-04

申请号：US16543124

申请日：2019-08-16

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Philippe Boivin ,  Jean-Jacques Fagot

IPC: H01L29/423 ,  H01L27/24 ,  H01L21/28 ,  H01L29/66 ,  H01L21/762 ,  H01L29/78 ,  H01L45/00

Abstract: A MOS transistor with two vertical gates is formed within a substrate zone of a semiconductor substrate doped with a first type of conductivity and separated from a remaining portion of the substrate by two first parallel trenches extending in a first direction. An isolated gate region rests on each flank of the substrate zone and on a portion of the bottom of the corresponding trench to form the two vertical gates. At least one gate connection region electrically connects the two vertical gates. A first buried region located under the substrate zone is doped with a second type of conductivity to form a first conduction electrode of the MOS transistor. A second region doped with the second type of conductivity is located at the surface of the substrate zone to form a second conduction electrode of the MOS transistor.

公开(公告)号：US11329067B2

公开(公告)日：2022-05-10

申请号：US16898700

申请日：2020-06-11

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Jean-Jacques Fagot ,  Philippe Boivin ,  Franck Arnaud

IPC: H01L27/12 ,  H01L21/762 ,  H01L29/808 ,  H01L21/84 ,  H01L27/06

Abstract: An electronic integrated circuit chip includes a first transistor arranged inside and on top of a solid substrate, a second transistor arranged inside and on top of a layer of semiconductor material on insulator having a first thickness, and a third transistor arranged inside and on top of a layer of semiconductor material on insulator having a second thickness. The second thickness is greater than the first thickness. The solid substrate extends underneath the layers of semiconductor material and is insulated from those layers by the insulator.

公开(公告)号：US10714501B2

公开(公告)日：2020-07-14

申请号：US16057466

申请日：2018-08-07

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Jean-Jacques Fagot ,  Philippe Boivin ,  Franck Arnaud

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/84 ,  H01L29/808 ,  H01L27/06

Abstract: An electronic integrated circuit chip includes a first transistor arranged inside and on top of a solid substrate, a second transistor arranged inside and on top of a layer of semiconductor material on insulator having a first thickness, and a third transistor arranged inside and on top of a layer of semiconductor material on insulator having a second thickness. The second thickness is greater than the first thickness. The solid substrate extends underneath the layers of semiconductor material and is insulated from those layers by the insulator.

公开(公告)号：US10431630B2

公开(公告)日：2019-10-01

申请号：US15436963

申请日：2017-02-20

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Philippe Boivin ,  Jean-Jacques Fagot

IPC: H01L27/24 ,  H01L21/762 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L45/00 ,  H01L21/28

Abstract: A MOS transistor with two vertical gates is formed within a substrate zone of a semiconductor substrate doped with a first type of conductivity and separated from a remaining portion of the substrate by two first parallel trenches extending in a first direction. An isolated gate region rests on each flank of the substrate zone and on a portion of the bottom of the corresponding trench to form the two vertical gates. At least one gate connection region electrically connects the two vertical gates. A first buried region located under the substrate zone is doped with a second type of conductivity to form a first conduction electrode of the MOS transistor. A second region doped with the second type of conductivity is located at the surface of the substrate zone to form a second conduction electrode of the MOS transistor.

公开(公告)号：US20180076265A1

公开(公告)日：2018-03-15

申请号：US15436963

申请日：2017-02-20

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Philippe Boivin ,  Jean-Jacques Fagot

IPC: H01L27/24 ,  H01L29/66 ,  H01L21/762 ,  H01L29/78 ,  H01L29/423 ,  H01L45/00

Abstract: A MOS transistor with two vertical gates is formed within a substrate zone of a semiconductor substrate doped with a first type of conductivity and separated from a remaining portion of the substrate by two first parallel trenches extending in a first direction. An isolated gate region rests on each flank of the substrate zone and on a portion of the bottom of the corresponding trench to form the two vertical gates. At least one gate connection region electrically connects the two vertical gates. A first buried region located under the substrate zone is doped with a second type of conductivity to form a first conduction electrode of the MOS transistor. A second region doped with the second type of conductivity is located at the surface of the substrate zone to form a second conduction electrode of the MOS transistor.