公开(公告)号：US11456853B2

公开(公告)日：2022-09-27

申请号：US16810434

申请日：2020-03-05

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Ibrahima Diop ,  Yanis Linge

IPC: H04L9/00 ,  G06F7/72 ,  G06F7/504 ,  G06F7/525

Abstract: Cryptographic circuitry, in operation, performs a calculation on a first number and a second number. The performing of the calculation is protected by breaking the second number into a plurality of third numbers, a sum of values of the third numbers being equal to a value of the second number. The calculation is performed bit by bit for each rank of the third numbers. Functional circuitry, coupled to the cryptographic circuitry, uses a result of the calculation.

公开(公告)号：US11049419B2

公开(公告)日：2021-06-29

申请号：US16186820

申请日：2018-11-12

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Sarafianos ,  Thomas Ordas ,  Yanis Linge

IPC: G09C1/00 ,  H03K19/003 ,  H04L9/00 ,  G06F21/75

Abstract: In an embodiment, a circuit includes a supply terminal, a reference terminal, a logic circuit coupled between the supply terminal and the reference terminal, and an auxiliary circuit coupled to the logic circuit. The auxiliary circuit includes a plurality of switches configured to be controlled to produce random criterions. Each random criterion causes, on each transition of an output signal of the logic, an attenuation of a current flowing between a supply terminal of the circuit and a reference terminal of the circuit; or an increase of the current flowing between the supply terminal of the circuit and the reference terminal of the circuit; or an additional current flowing through the logic circuit on a current path not passing through the supply terminal; or no change in the current flowing between the supply terminal of the circuit and the reference terminal of the circuit.

公开(公告)号：US10769513B2

公开(公告)日：2020-09-08

申请号：US16227525

申请日：2018-12-20

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Sarafianos ,  Thomas Ordas ,  Yanis Linge ,  Jimmy Fort

IPC: G06K19/073 ,  G06F21/75 ,  G06F21/44 ,  H01L23/00

Abstract: An electronic device includes a logic circuit and an auxiliary circuit. The logic circuit includes a first terminal coupled to a supply voltage terminal, a second terminal intended coupled to a reference voltage terminal and an output terminal configured to deliver a signal in a high state or a low state. The auxiliary circuit is coupled between the first terminal and the second terminal and is configured to randomly generate or not generate an additional current between the first terminal and the second terminal on each change of state of the signal on the output terminal.

公开(公告)号：US10354063B2

公开(公告)日：2019-07-16

申请号：US15442303

申请日：2017-02-24

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Ibrahima Diop ,  Pierre-Yvan Liardet ,  Yanis Linge

IPC: G06F21/52 ,  G06F7/523 ,  G06F7/72

Abstract: A method of protecting a modular calculation on a first number and a second number, executed by an electronic circuit, including the steps of: combining the second number with a third number to obtain a fourth number; executing the modular calculation on the first and fourth numbers, the result being contained in a first register or memory location; initializing a second register or memory location to the value of the first register or to one; and successively, for each bit at state 1 of the third number: if the corresponding bit of the fourth number is at state 1, multiplying the content of the second register or memory location by the inverse of the first number and placing the result in the first register or memory location, if the corresponding bit of the fourth number is at state 0, multiplying the content of the second register or memory location by the first number and placing the result in the first register or memory location.

公开(公告)号：US11436346B2

公开(公告)日：2022-09-06

申请号：US16866088

申请日：2020-05-04

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Fabien Journet ,  Yanis Linge

IPC: G06F21/60 ,  G06F9/30 ,  G06F21/84 ,  H04L9/08

Abstract: A method and device for protecting encrypted data are disclosed. In an embodiment an integrated circuit includes a secure module including a first register containing a first mask and a second register containing masked data, the first mask and the masked data forming a secret key and a processor configured to generate a second mask and mask the secret key with the second mask when the secret key is not used for an encryption operation and during reception of a validation signal, wherein the first and second registers are disposed in the secure module so that the outputs of the registers are not simultaneously optically viewable.

公开(公告)号：US11329796B2

公开(公告)日：2022-05-10

申请号：US16435307

申请日：2019-06-07

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Ibrahima Diop ,  Yanis Linge

IPC: H04L9/00 ,  G06F7/72 ,  G06F21/72

Abstract: A calculation is performed on a first number and a second number. For each bit of the second number a first function is performed. The first function inputs include contents of a first register, contents of a second register and the first number. A result of the first function is placed in a third register. For each bit of the second number, a second function is performed which has as inputs contents of the third register and the contents of a selected one of the first and the second register according to a state of a current bit of the second number. A result of the second function is stored in the selected one of the first and second register.

公开(公告)号：US11265145B2

公开(公告)日：2022-03-01

申请号：US16281881

申请日：2019-02-21

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Yanis Linge ,  Thomas Ordas ,  Pierre-Yvan Liardet

IPC: H04L9/06 ,  H04L9/00

Abstract: The disclosure concerns implementing, by a cryptographic circuit, a set of substitution operations of a cryptographic process involving a plurality of substitution tables. For each set of substitution operations of the cryptographic process, a series of sets of substitution operations are performed. One set of the series is a real set of substitution operations corresponding to the set of substitution operations of the cryptographic process. One or more other sets are dummy sets of substitution operations, each dummy set being based on a different permutation of said substitution tables.

公开(公告)号：US11265142B2

公开(公告)日：2022-03-01

申请号：US16435309

申请日：2019-06-07

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Ibrahima Diop ,  Yanis Linge

IPC: H04L9/00 ,  G06F21/72 ,  G06F7/72

Abstract: The disclosure concerns a method of protecting a calculation on a first number and a second number, including the steps of: generating a third number including at least the bits of the second number, the number of bits of the third number being an integer multiple of a fourth number; dividing the third number into blocks each having the size of the fourth number; successively, for each block of the third number: performing a first operation with a first operator on the contents of a first register and of a second register, and then on the obtained intermediate result and the first number, and placing the result in a third register; and for each bit of the current block, performing a second operation by submitting the content of the third register to a second operator with a function of the rank of the current bit of the third number, and then to the first operator with the content of the first or of the second register according to state “0” or “1” of said bit, and placing the result in the first or second register.

公开(公告)号：US11218291B2

公开(公告)日：2022-01-04

申请号：US16281889

申请日：2019-02-21

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Thomas Ordas ,  Yanis Linge

IPC: H04L9/06 ,  G06F21/72

Abstract: A cryptographic circuit performs a substitution operation of a cryptographic algorithm. For each substitution operation of the cryptographic algorithm, a series of substitution operations are performed by the cryptographic circuit. One of the substitution operations of the series is a real substitution operation corresponding to the substitution operation of the cryptographic algorithm. One or more other substitution operations of the series are dummy substitution operations. A position of the real substitution operation in said series is selected randomly.

公开(公告)号：US10977365B2

公开(公告)日：2021-04-13

申请号：US16041077

申请日：2018-07-20

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Ibrahima Diop ,  Yanis Linge ,  Pierre-Yvan Liardet

IPC: G06F21/00 ,  G06F21/55 ,  G06F21/60 ,  G06F7/72 ,  H04L9/00 ,  G06F21/72

Abstract: An iterative calculation is performed on a first number and a second number, while protecting the iterative calculation against side-channel attacks. For each bit of the second number, successively, an iterative calculation routine of the bit of the second number is determined. The determination is made independent of a state of the bit. The determined iterative calculation routine of the bit is executed. A result of the iterative calculation is generated based on a result of the execution of the determined iterative calculation routine of a last bit of the second number.