公开(公告)号：US10949572B2

公开(公告)日：2021-03-16

申请号：US16411819

申请日：2019-05-14

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Sarafianos ,  Thomas Ordas ,  Yanis Linge ,  Jimmy Fort

IPC: G06F21/75 ,  H04L9/00 ,  G06F30/327

Abstract: The supply voltage for a module of an integrated circuit managed to support protection against side channel attacks. Upon startup of the integrated circuit, one action from the following actions is selected in response to a command: supplying the module with the supply voltage having a fixed value that is selected from a plurality of predetermined values, or varying the value of the supply voltage in time with a pulsed signal.

公开(公告)号：US20200020650A1

公开(公告)日：2020-01-16

申请号：US16503876

申请日：2019-07-05

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Sarafianos ,  Bruno Nicolas ,  Daniele Fronte

IPC: H01L23/00

Abstract: An electronic chip includes a first well having a first PN junction located therein, a second buried well located under and separated from the first well, and a first region forming a second PN junction with the second well. A detection circuit is coupled to the first well and configured to output a digital signal that has a first logic value when a potential difference within the first region is above a threshold and a second logic value when the potential difference within the first region is below the threshold.

公开(公告)号：US20180341788A1

公开(公告)日：2018-11-29

申请号：US15920835

申请日：2018-03-14

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Sarafianos ,  Thomas Ordas

IPC: G06F21/76 ,  G11C19/28 ,  H03K19/003 ,  H03K19/21 ,  H03K19/20

Abstract: A device can be used for detecting faults. A shift register is suitable for shifting, in tempo with a clock, a binary signal alternating between two logic levels, in successive cells of the shift register. A first logic circuit is suitable for comparing values contained in at least one pair of cells of the register.

公开(公告)号：US20180189624A1

公开(公告)日：2018-07-05

申请号：US15798553

申请日：2017-10-31

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Sarafianos ,  Thomas Ordas ,  Yanis Linge ,  Jimmy Fort

IPC: G06K19/073 ,  H01L23/00 ,  G06F21/44

CPC classification number: G06K19/07363 ,  G06F21/445 ,  G06F21/75 ,  G06F21/755 ,  H01L23/576 ,  H01L2224/48228

Abstract: An electronic device includes a logic circuit and an auxiliary circuit. The logic circuit includes a first terminal coupled to a supply voltage terminal, a second terminal intended coupled to a reference voltage terminal and an output terminal configured to deliver a signal in a high state or a low state. The auxiliary circuit is coupled between the first terminal and the second terminal and is configured to randomly generate or not generate an additional current between the first terminal and the second terminal on each change of state of the signal on the output terminal.

公开(公告)号：US20170338824A1

公开(公告)日：2017-11-23

申请号：US15627157

申请日：2017-06-19

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Sarafianos ,  Bruno Nicolas

IPC: H03K19/177 ,  H03K19/003 ,  H01L23/00

CPC classification number: H03K19/17768 ,  G06F21/75 ,  G06F21/87 ,  G09C1/00 ,  H01L23/576 ,  H03K19/0033 ,  H03K19/17704 ,  H04L9/004 ,  H04L2209/12

Abstract: An integrated circuit protection device, including: groups of radiation detection elements distributed in a matrix array; logic gates combining outputs of the detection elements in rows and in columns, each output of a detection element being connected to a gate combining a row and to a gate combining a column; and a circuit for interpreting signals supplied by said logic gates and including an event counter and a delay element.

公开(公告)号：US20170116439A1

公开(公告)日：2017-04-27

申请号：US15137789

申请日：2016-04-25

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Sarafianos ,  Jimmy Fort ,  Clement Champeix ,  Jean-Max Dutertre ,  Nicolas Borrel

IPC: G06F21/86 ,  H03K5/153 ,  H03K5/24 ,  H01L23/00

CPC classification number: G06F21/86 ,  G09C1/00 ,  H01L23/576 ,  H03K5/153 ,  H03K5/24 ,  H04L9/004 ,  H04L2209/12

Abstract: A secure electronic chip including a plurality of biased semiconductor wells and a well biasing current detection circuit. Each of the wells includes a transistor and a bias contact electrically isolated from the transistor. The detection circuit is electrically coupled to each bias contact and is configured to detect a bias current passing through the bias contact that is indicative of an attempt to tamper with the electronic chip.

公开(公告)号：US11387194B2

公开(公告)日：2022-07-12

申请号：US15930217

申请日：2020-05-12

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Sarafianos ,  Fabrice Marinet ,  Julien Delalleau

IPC: H01L23/00 ,  G06F21/55

Abstract: A semiconductor substrate has a front face and a back face. A first contact and a second contact, spaced apart from each other, are located on the front face. An electrically conductive wafer is located on the back face. A detection circuit is configured to detect a thinning of the substrate from the back face. The detection circuit including a measurement circuit that takes a measurement of a resistive value of the substrate between said at least one first contact, said at least one second contact and said electrically conductive wafer. Thinning is detected in response to the measured resistive value.

公开(公告)号：US11011479B2

公开(公告)日：2021-05-18

申请号：US16503876

申请日：2019-07-05

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Sarafianos ,  Bruno Nicolas ,  Daniele Fronte

IPC: H01L23/00

Abstract: An electronic chip includes a first well having a first PN junction located therein, a second buried well located under and separated from the first well, and a first region forming a second PN junction with the second well. A detection circuit is coupled to the first well and configured to output a digital signal that has a first logic value when a potential difference within the first region is above a threshold and a second logic value when the potential difference within the first region is below the threshold.

公开(公告)号：US10691840B2

公开(公告)日：2020-06-23

申请号：US15137789

申请日：2016-04-25

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Sarafianos ,  Jimmy Fort ,  Clement Champeix ,  Jean-Max Dutertre ,  Nicolas Borrel

IPC: G06F21/86 ,  G09C1/00 ,  H04L9/00 ,  H01L23/00 ,  H03K5/153 ,  H03K5/24

Abstract: A secure electronic chip including a plurality of biased semiconductor wells and a well biasing current detection circuit. Each of the wells includes a transistor and a bias contact electrically isolated from the transistor. The detection circuit is electrically coupled to each bias contact and is configured to detect a bias current passing through the bias contact that is indicative of an attempt to tamper with the electronic chip.

公开(公告)号：US20190051723A1

公开(公告)日：2019-02-14

申请号：US16161785

申请日：2018-10-16

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Clement Champeix ,  Nicolas Borrel ,  Alexandre Sarafianos

IPC: H01L29/06 ,  H03K5/24 ,  H01L23/00 ,  G06F21/77 ,  G06F21/78 ,  H01L29/10 ,  H01L27/092 ,  H01L27/06 ,  G06F21/75 ,  G06F21/88 ,  G06F21/87 ,  H01L29/66

CPC classification number: H01L29/0623 ,  G06F21/75 ,  G06F21/77 ,  G06F21/78 ,  G06F21/87 ,  G06F21/88 ,  H01L21/823892 ,  H01L23/57 ,  H01L23/576 ,  H01L27/0629 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/107 ,  H01L29/1095 ,  H01L29/66181 ,  H03K5/24

Abstract: An electronic chip includes a doped semiconductor substrate of a first conductivity type, a doped buried layer of a second conductivity type overlying the substrate, and a first doped well of the first conductivity type overlying the buried layer. Circuit components can be formed at a top surface of the first doped well and separated from the buried layer. A current detector is coupled to the buried layer and configured detect a bias current flowing into or out of the buried layer.