公开(公告)号：US10977365B2

公开(公告)日：2021-04-13

申请号：US16041077

申请日：2018-07-20

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Ibrahima Diop ,  Yanis Linge ,  Pierre-Yvan Liardet

IPC: G06F21/00 ,  G06F21/55 ,  G06F21/60 ,  G06F7/72 ,  H04L9/00 ,  G06F21/72

Abstract: An iterative calculation is performed on a first number and a second number, while protecting the iterative calculation against side-channel attacks. For each bit of the second number, successively, an iterative calculation routine of the bit of the second number is determined. The determination is made independent of a state of the bit. The determined iterative calculation routine of the bit is executed. A result of the iterative calculation is generated based on a result of the execution of the determined iterative calculation routine of a last bit of the second number.

公开(公告)号：US20180060566A1

公开(公告)日：2018-03-01

申请号：US15442303

申请日：2017-02-24

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Ibrahima Diop ,  Pierre-Yvan Liardet ,  Yanis Linge

IPC: G06F21/52 ,  G06F7/72 ,  G06F7/523

CPC classification number: G06F21/52 ,  G06F7/523 ,  G06F7/72 ,  G06F7/723 ,  G06F2207/7242 ,  G06F2221/032

Abstract: A method of protecting a modular calculation on a first number and a second number, executed by an electronic circuit, including the steps of: combining the second number with a third number to obtain a fourth number; executing the modular calculation on the first and fourth numbers, the result being contained in a first register or memory location; initializing a second register or memory location to the value of the first register or to one; and successively, for each bit at state 1 of the third number: if the corresponding bit of the fourth number is at state 1, multiplying the content of the second register or memory location by the inverse of the first number and placing the result in the first register or memory location, if the corresponding bit of the fourth number is at state 0, multiplying the content of the second register or memory location by the first number and placing the result in the first register or memory location.

公开(公告)号：US11456853B2

公开(公告)日：2022-09-27

申请号：US16810434

申请日：2020-03-05

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Ibrahima Diop ,  Yanis Linge

IPC: H04L9/00 ,  G06F7/72 ,  G06F7/504 ,  G06F7/525

Abstract: Cryptographic circuitry, in operation, performs a calculation on a first number and a second number. The performing of the calculation is protected by breaking the second number into a plurality of third numbers, a sum of values of the third numbers being equal to a value of the second number. The calculation is performed bit by bit for each rank of the third numbers. Functional circuitry, coupled to the cryptographic circuitry, uses a result of the calculation.

公开(公告)号：US10354063B2

公开(公告)日：2019-07-16

申请号：US15442303

申请日：2017-02-24

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Ibrahima Diop ,  Pierre-Yvan Liardet ,  Yanis Linge

IPC: G06F21/52 ,  G06F7/523 ,  G06F7/72

Abstract: A method of protecting a modular calculation on a first number and a second number, executed by an electronic circuit, including the steps of: combining the second number with a third number to obtain a fourth number; executing the modular calculation on the first and fourth numbers, the result being contained in a first register or memory location; initializing a second register or memory location to the value of the first register or to one; and successively, for each bit at state 1 of the third number: if the corresponding bit of the fourth number is at state 1, multiplying the content of the second register or memory location by the inverse of the first number and placing the result in the first register or memory location, if the corresponding bit of the fourth number is at state 0, multiplying the content of the second register or memory location by the first number and placing the result in the first register or memory location.

公开(公告)号：US11329796B2

公开(公告)日：2022-05-10

申请号：US16435307

申请日：2019-06-07

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Ibrahima Diop ,  Yanis Linge

IPC: H04L9/00 ,  G06F7/72 ,  G06F21/72

Abstract: A calculation is performed on a first number and a second number. For each bit of the second number a first function is performed. The first function inputs include contents of a first register, contents of a second register and the first number. A result of the first function is placed in a third register. For each bit of the second number, a second function is performed which has as inputs contents of the third register and the contents of a selected one of the first and the second register according to a state of a current bit of the second number. A result of the second function is stored in the selected one of the first and second register.

公开(公告)号：US11265142B2

公开(公告)日：2022-03-01

申请号：US16435309

申请日：2019-06-07

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Ibrahima Diop ,  Yanis Linge

IPC: H04L9/00 ,  G06F21/72 ,  G06F7/72

Abstract: The disclosure concerns a method of protecting a calculation on a first number and a second number, including the steps of: generating a third number including at least the bits of the second number, the number of bits of the third number being an integer multiple of a fourth number; dividing the third number into blocks each having the size of the fourth number; successively, for each block of the third number: performing a first operation with a first operator on the contents of a first register and of a second register, and then on the obtained intermediate result and the first number, and placing the result in a third register; and for each bit of the current block, performing a second operation by submitting the content of the third register to a second operator with a function of the rank of the current bit of the third number, and then to the first operator with the content of the first or of the second register according to state “0” or “1” of said bit, and placing the result in the first or second register.

公开(公告)号：US10025559B2

公开(公告)日：2018-07-17

申请号：US15442322

申请日：2017-02-24

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Ibrahima Diop ,  Yanis Linge ,  Pierre-Yvan Liardet

IPC: G06F7/58 ,  G06F7/72 ,  G06F21/72

Abstract: A method of protecting a modular exponentiation calculation on a first number and an exponent, modulo a first modulo, executed by an electronic circuit using a first register or memory location and a second register or memory location, successively including, for each bit of the exponent: generating a random number; performing a modular multiplication of the content of the first register or memory location by that of the second register or memory location, and placing the result in one of the first and second registers or memory locations selected according to the state of the bit of the exponent; performing a modular squaring of the content of one of the first and second registers or memory locations selected according to the state of the exponent, and placing the result in this selected register or memory location, the multiplication and squaring operations being performed modulo the product of the first modulo by said random number.

公开(公告)号：US20180060040A1

公开(公告)日：2018-03-01

申请号：US15442322

申请日：2017-02-24

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Ibrahima Diop ,  Yanis Linge ,  Pierre-Yvan Liardet

IPC: G06F7/72 ,  G06F7/58

CPC classification number: G06F7/723 ,  G06F7/58 ,  G06F7/722 ,  G06F21/72 ,  G06F2207/7247

Abstract: A method of protecting a modular exponentiation calculation on a first number and an exponent, modulo a first modulo, executed by an electronic circuit using a first register or memory location and a second register or memory location, successively including, for each bit of the exponent: generating a random number; performing a modular multiplication of the content of the first register or memory location by that of the second register or memory location, and placing the result in one of the first and second registers or memory locations selected according to the state of the bit of the exponent; performing a modular squaring of the content of one of the first and second registers or memory locations selected according to the state of the exponent, and placing the result in this selected register or memory location, the multiplication and squaring operations being performed modulo the product of the first modulo by said random number.