公开(公告)号：US20190279707A1

公开(公告)日：2019-09-12

申请号：US16351773

申请日：2019-03-13

Applicant: STMicroelectronics International N.V.

Inventor： Abhishek PATHAK ,  Tanmoy ROY ,  Shishir KUMAR

IPC: G11C11/412 ,  G11C7/14 ,  G11C11/419

Abstract: A memory device includes first and second dummy word line portions. A dummy word line driver drives the first dummy word line portion. A voltage dropping circuit causes a voltage on the second dummy word line to be less than a voltage on the first dummy word line. At least one dummy memory cell is coupled to the second dummy word line portion, remains in standby until assertion of the second dummy word line, and performs a dummy cycle in response to assertion of the second dummy word line. A reset signal generation circuit generates a reset signal in response to completion of a dummy cycle by the at least one dummy memory cell. An internal clock signal is generated from an external clock signal and the reset signal and is used in performing a read and/or write cycle to a memory array.

公开(公告)号：US20200243153A1

公开(公告)日：2020-07-30

申请号：US16742292

申请日：2020-01-14

Applicant: STMicroelectronics International N.V.

Inventor： Shishir KUMAR ,  Abhishek PATHAK

IPC: G11C29/38 ,  G11C8/10 ,  G11C29/44

Abstract: A row decoder located on one side of a memory array selectively drives word lines in response to a row address. A word line fault detection circuit located on an opposite side of the first memory array operates to detect an open word line fault between the opposed sides of the memory array. The word line fault detection circuit includes a first clamp circuit that operates to clamp the word lines to ground. An encoder circuit encodes signals on the word lines to generate an encoded address. The encoded address is compared to the row address by a comparator circuit which sets an error flag indicating the open word line fault has been detected if the encoded address does not match the row address.