公开(公告)号：US20160315611A1

公开(公告)日：2016-10-27

申请号：US14697461

申请日：2015-04-27

Applicant: STMicroelectronics International N.V.

Inventor： Vikas RANA ,  Amit CHHABRA

IPC: H03K17/687 ,  H01L23/50 ,  H01L23/34 ,  H01L27/12 ,  H01L27/092

CPC classification number: H03K17/693 ,  H01L27/092 ,  H01L27/1203 ,  H03K17/005 ,  H03K2217/0018

Abstract: An integrated circuit die includes a plurality of transistors formed in a semiconductor substrate, the body regions of the transistors on a doped well region of the semiconductor substrate. A body bias voltage generator generates a positive body bias voltage, and a negative body bias voltage in the ground body bias voltage. A multiplexer selectively outputs one of the positive, negative, or ground body bias voltage to the doped well region of the semiconductor substrate based on the temperature of the semiconductor substrate.

Abstract translation: 集成电路管芯包括形成在半导体衬底中的多个晶体管，在半导体衬底的掺杂阱区域上的晶体管的体区。 体偏置电压发生器产生正的体偏置电压和负体偏置电压的接地体偏置电压。 复用器基于半导体衬底的温度，将正，负或接地体偏置电压中的一个选择性地输出到半导体衬底的掺杂阱区。

公开(公告)号：US20160012867A1

公开(公告)日：2016-01-14

申请号：US14329747

申请日：2014-07-11

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Amit CHHABRA

IPC: G11C5/14 ,  G05F1/46

CPC classification number: G11C5/148 ,  G05F1/46 ,  G05F1/465 ,  H03K3/0377 ,  H03K5/082 ,  H03K17/223

Abstract: A dual-rail memory circuit having a sleep generation circuit configured to prevent undesired currents from being generated during power-up and while transitioning power states. When a dual-rail memory circuit is powering-up or exiting from a sleep mode, the ramping up of various supply voltage nodes may occur at different rates. Thus, in a dual-rail memory circuit, a first voltage rail may be at voltage before a second voltage rail. Such a transient state of operation may lead to current spikes that unnecessarily draw power and introduce undesired inefficiency. An internal sleep signal generation circuit in a dual-rail memory circuit may be used to precisely control an internal sleep signal such that the transition from off or sleep mode to operating mode is set to assure that the supply voltage nodes are close enough to the at-voltage operating level before releasing the sleep mode.

Abstract translation: 具有睡眠产生电路的双轨存储器电路，其被配置为防止在上电期间和在转换功率状态期间产生不期望的电流。 当双轨存储器电路上电或从睡眠模式退出时，各种电源节点的升高可以以不同的速率发生。 因此，在双轨存储器电路中，第一电压轨可以在第二电压轨之前处于电压。 这种瞬时的操作状态可能导致电流尖峰不必要地抽取功率并引入不期望的低效率。 双轨存储器电路中的内部睡眠信号产生电路可以用于精确地控制内部睡眠信号，使得从关闭或休眠模式到操作模式的转变被设置为确保电源电压节点足够接近于at - 释放睡眠模式前的电压工作电平。