-
公开(公告)号:US20240030908A1
公开(公告)日:2024-01-25
申请号:US18209441
申请日:2023-06-13
发明人: Hailing Wang , Dylan Charles Bartle , Hanching Fuh , Jerod F. Mason , David Scott Whitefield , Paul T. DiCarlo
CPC分类号: H03K17/161 , H03K17/102 , H03K17/122 , H03K17/693 , H01L23/66 , H01L27/1203 , H03K2217/0018 , H01L2223/6677 , H04B1/38
摘要: Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of auxiliary FETs coupled in series and a main FET coupled in parallel with an interior FET of the plurality of auxiliary FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.
-
公开(公告)号:US20230299761A1
公开(公告)日:2023-09-21
申请号:US17897845
申请日:2022-08-29
发明人: Shigeo IMAI
CPC分类号: H03K17/063 , H03K17/162 , H03K2217/0018
摘要: An analog switch circuit of an embodiment includes a CMOS analog switch, a first gate drive circuit, and a second gate drive circuit, a gate operating withstand voltage of the CMOS analog switch being VGT, an enable signal and a control signal being inputted to the first gate drive circuit and the second gate drive circuit. Assuming that VGT
-
公开(公告)号:US20190036524A1
公开(公告)日:2019-01-31
申请号:US16132286
申请日:2018-09-14
IPC分类号: H03K17/16 , H03K17/693 , H02M3/07 , H03K5/08 , H03K19/0185 , G05F3/20 , H03K17/10 , H04B1/48
CPC分类号: H03K17/162 , G05F3/205 , H02M3/07 , H03K5/08 , H03K17/102 , H03K17/693 , H03K19/018507 , H03K2217/0018 , H03K2217/0081 , H04B1/48
摘要: A switch control circuit includes a positive voltage bias node, a voltage-regulated positive supply rail coupled to the positive voltage bias node, a charge pump coupled to a charge pump supply node, and a current source positive supply rail coupled to the charge pump supply node and configured to supply the charge pump.
-
公开(公告)号:US20190013807A1
公开(公告)日:2019-01-10
申请号:US15861200
申请日:2018-01-03
申请人: NXP USA, Inc.
IPC分类号: H03K17/687 , H01L29/78 , H01L21/8234 , H01L29/08
CPC分类号: H03K17/6871 , H01L21/823487 , H01L29/086 , H01L29/0878 , H01L29/7813 , H03K17/08142 , H03K2217/0009 , H03K2217/0018
摘要: A body-control-device for a bi-directional transistor, said bi-directional transistor having a first-transistor-channel-terminal, a second-transistor-channel-terminal, a transistor-control-terminal and a transistor-body-terminal. The body-control-device comprises a body-control-terminal connectable to the transistor-body-terminal of the bi-directional transistor, a first-body-channel-terminal connectable to the first-transistor-channel-terminal of the bi-directional transistor, a second-body-channel-terminal connectable to the second-transistor-channel-terminal of the bi-directional transistor, a negative-voltage-source and a switching-circuit configured to selectively provide an offset-first-circuit-path between the first-body-channel-terminal and the body-control-terminal, wherein the offset-first-circuit-path includes the negative-voltage-source such that it provides a negative voltage bias between the body-control-terminal and the first-body-channel-terminal.
-
公开(公告)号:US20180343006A1
公开(公告)日:2018-11-29
申请号:US15990034
申请日:2018-05-25
IPC分类号: H03K17/687 , H01L29/78 , H01L29/47 , H01L29/739 , H01L29/772 , H01L29/49 , H01L29/51 , H01L29/24 , H01L29/66
CPC分类号: H03K17/687 , H01L29/24 , H01L29/47 , H01L29/495 , H01L29/517 , H01L29/66969 , H01L29/7391 , H01L29/7722 , H01L29/7831 , H01L29/7839 , H01L29/786 , H03K2017/6878 , H03K2217/0018
摘要: The field effect transistor (FET) of the present subject matter comprises a bottom gate electrode, a bottom gate dielectric provided on the bottom gate electrode, a channel layer provided on the bottom gate dielectric. A top portion comprising a source electrode, a drain electrode, a top gate electrode provided, and a top dielectric layer is provided on the channel layer. The channel layer forms Schottky barriers at points of contact with the source and the drain electrode. A back-gate voltage varies a height and a top-gate voltage varies a width of the Schottky barrier. The FET can be programmed to work in two operating modes-tunnelling (providing low power consumption) and thermionic mode (providing high performance). The FET can also be programmed to combine the tunnelling and thermionic mode in a single operating cycle, yielding high performance with low power consumption.
-
公开(公告)号:US20180167065A1
公开(公告)日:2018-06-14
申请号:US15840043
申请日:2017-12-13
发明人: On Bon Peter CHAN
IPC分类号: H03K17/567
CPC分类号: H03K17/567 , H03K17/06 , H03K17/687 , H03K2017/307 , H03K2017/6875 , H03K2217/0018 , H03K2217/0081
摘要: A bootstrap diode emulator circuit having a cathode and an anode includes a transistor device and a diodic device. The transistor device is arranged at the cathode of the bootstrap diode emulator circuit. The diodic device has a cathode connected to the transistor device and an anode that is the anode of the bootstrap diode emulator circuit.
-
公开(公告)号:US09991776B2
公开(公告)日:2018-06-05
申请号:US15139921
申请日:2016-04-27
发明人: Jaume Roig-Guitart , Filip Bauwens
IPC分类号: H02M1/08 , H02M3/158 , H03K17/10 , H03K17/687 , H03K17/74
CPC分类号: H02M1/08 , H02M3/158 , H03K17/102 , H03K17/6871 , H03K17/74 , H03K2017/6875 , H03K2217/0018
摘要: A method and apparatus for switched mode power supply (SMPS) system includes circuitry configured to produce a voltage output based on an input voltage, the SMPS circuitry includes inductive, capacitive and switching elements configured to generate the voltage output. The switching elements include at least one set of cascode coupled devices, each set of cascode coupled devices including a high electron mobility transistor (HEMT) and one of a diode and a field effect transistor (FET) in a cascode coupling. A controller produces a signal to a gate terminal of the FET of the sets of cascode coupled devices to drive the HEMT switching rate to adjust the output voltage. The circuitry of the SMPS further includes circuitry to couple the substrate of at least one HEMT to a high voltage node of the SMPS system to reduce large voltage spikes or dv/dts.
-
公开(公告)号:US09966793B2
公开(公告)日:2018-05-08
申请号:US15646085
申请日:2017-07-10
申请人: NXP USA, Inc.
发明人: Ashita Batra , Mayank Jain
IPC分类号: H02J1/10 , H02J9/06 , H03K17/687 , H03K17/693
CPC分类号: H02J9/061 , H02J1/10 , H03K17/687 , H03K17/693 , H03K2217/0018 , Y10T307/625
摘要: A system for providing a first voltage generated by a main supply and a second voltage generated by a battery to an integrated circuit (IC) includes supply-selection, control logic and switching circuits. The supply-selection circuit includes first, second, and third transistors. The switching circuit includes fourth and fifth transistors that supply the first and second voltages to the IC when switched on. The supply-selection circuit selects and provides the higher of the first and second voltages to body terminals of the fourth and fifth transistors for maintaining required body-bias voltage conditions. The control logic circuit generates a first control signal as long as the first voltage is within a predetermined range for keeping the fourth transistor switched on and a second control signal when the first voltage is not within the predetermined range for switching on the fifth transistor to supply the second voltage.
-
公开(公告)号:US20180123585A1
公开(公告)日:2018-05-03
申请号:US15706121
申请日:2017-09-15
发明人: Gregory BUNIN , David Shapiro , Lev Stessin
IPC分类号: H03K17/687 , H03K7/08
CPC分类号: H03K17/687 , H01L29/1075 , H01L29/2003 , H01L29/7786 , H03K7/08 , H03K17/102 , H03K17/145 , H03K2217/0018
摘要: An apparatus includes a circuitry to perform a high current and/or a high voltage switching. The circuitry includes a first Gallium Nitride (GaN) on a silicon (Si) substrate lateral field effect transistor. A source terminal of the first GaN lateral field effect transistor on the Si substrate includes an electrical connection to backside of P-type Si substrate through a high voltage isolated resistor that is coupled to a source terminal or a second resistor that is operably coupled to a drain terminal and a substrate terminal. The high voltage isolated resistor and the second resistor cause to a leakage current from the drain terminal to the source terminal via a buffer layer. The leakage current equalizes the voltage drop on the first GaN lateral field effect transistor on the Si substrate to a voltage drop on a serially connected second GaN lateral field effect transistor on the Si substrate.
-
公开(公告)号:US09912329B2
公开(公告)日:2018-03-06
申请号:US15390020
申请日:2016-12-23
发明人: Ikuo Fukami
IPC分类号: H03K3/00 , H03K17/081 , H02P7/28 , H01L27/088 , H02M3/07
CPC分类号: H03K17/08104 , H01L27/088 , H01L27/0883 , H02M3/07 , H02P7/28 , H03K17/063 , H03K17/162 , H03K17/168 , H03K17/687 , H03K17/731 , H03K17/732 , H03K2217/0018 , H03K2217/0081
摘要: A semiconductor device includes a high side driver, in which the high side driver has an output transistor configured to supply a power voltage to an output terminal based on a driving voltage applied to a gate electrode of the output transistor; a short circuit transistor configured to couple the gate electrode of the output transistor with the output terminal; and a switch transistor connected in series between the gate electrode of the output transistor and a drain electrode of the short circuit transistor. The switch transistor is controlled by a back gate of the switch transistor.
-
-
-
-
-
-
-
-
-