公开(公告)号：US10386412B2

公开(公告)日：2019-08-20

申请号：US15678016

申请日：2017-08-15

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Saurabh Kumar Singh ,  Balwant Singh

IPC: G01R31/317

Abstract: A test circuit measures both the rising edge delay and the falling edge delay associated with a logic cell. The test circuit includes a flip-flop type ring oscillator with two groups of logic cells connected in series in the oscillation path. A first multiplexor switches the ring oscillator between a rising edge and a falling edge mode. A second multiplexer causes the second group of logic cells to be included or excluded from the oscillation path. By measuring the oscillation period in the various modes, the rising edge and falling edge delays can be individually calculated.

公开(公告)号：US09804225B2

公开(公告)日：2017-10-31

申请号：US14472220

申请日：2014-08-28

Applicant: STMicroelectronics International N.V.

Inventor： Saurabh Kumar Singh ,  Balwant Singh

IPC: G01R31/28 ,  G01R31/317

CPC classification number: G01R31/31725

Abstract: A test circuit measures both the rising edge delay and the falling edge delay associated with a logic cell. The test circuit includes a flip-flop type ring oscillator with two groups of logic cells connected in series in the oscillation path. A first multiplexor switches the ring oscillator between a rising edge and a falling edge mode. A second multiplexer causes the second group of logic cells to be included or excluded from the oscillation path. By measuring the oscillation period in the various modes, the rising edge and falling edge delays can be individually calculated.

公开(公告)号：US20160061894A1

公开(公告)日：2016-03-03

申请号：US14472220

申请日：2014-08-28

Applicant: STMicroelectronics International N.V.

Inventor： Saurabh Kumar Singh ,  Balwant Singh

IPC: G01R31/317 ,  G01R31/3177

CPC classification number: G01R31/31725

Abstract: A test circuit measures both the rising edge delay and the falling edge delay associated with a logic cell. The test circuit includes a flip-flop type ring oscillator with two groups of logic cells connected in series in the oscillation path. A first multiplexor switches the ring oscillator between a rising edge and a falling edge mode. A second multiplexer causes the second group of logic cells to be included or excluded from the oscillation path. By measuring the oscillation period in the various modes, the rising edge and falling edge delays can be individually calculated.

Abstract translation: 测试电路测量与逻辑单元相关联的上升沿延迟和下降沿延迟。 测试电路包括具有在振荡路径中串联连接的两组逻辑单元的触发器型环形振荡器。 第一个多路复用器在上升沿和下降沿模式之间切换环形振荡器。 第二多路复用器使第二组逻辑单元从振荡路径中包含或排除。 通过测量各种模式下的振荡周期，可以单独计算上升沿和下降沿延迟。