公开(公告)号：US20240402241A1

公开(公告)日：2024-12-05

申请号：US18203737

申请日：2023-05-31

Applicant: STMicroelectronics International N.V.

Inventor： Sandor PETENYI ,  Lukas BURIAN

IPC: G01R31/28 ,  G01R27/08

Abstract: Disclosed herein is a testing circuit for indirectly testing generation of a power-on-reset signal within an integrated circuit (IC). The testing circuit includes a switch configured to selectively disconnect an internal circuit from a test pin of the IC in response to start-up of the IC, a plurality of resistors connected between the test pin and a respective plurality of switches that are configured to selectively connect ones of the plurality of resistors to ground in response to corresponding control signals, and a control circuit configured to produce, at the test pin, a resistance indicative of status of generation of the POR signal by selectively operating the plurality of switches based upon statuses of a plurality of signals from which the POR signal is generated.