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公开(公告)号：US11513544B1
公开(公告)日：2022-11-29
申请号：US17537010
申请日：2021-11-29
Applicant: STMicroelectronics International N.V.
Inventor： Venkata Narayanan Srinivasan , Mayankkumar Hareshbhai Niranjani , Dhulipalla Phaneendra Kumar , Gourav Garg , Sourabh Banzal
Abstract: An electric device includes: a first power domain; a second power domain; a third power domain, where during power-up, the third, the second, and the first power domains are configured to be powered up sequentially, where during standby-exit, the first, the second, and the third power domains are configured to be powered up sequentially; isolation paths that provide controlled signal transmission among the first, the second, and the third power domains, where each isolation path includes an isolation circuit between an input power domain and an output power domain of the isolation path; and a control circuit in the first power domain, where for each isolation path, the control circuit is configured to generate an isolation control signal for the isolation circuit, where the isolation circuit is configured enable or disable signal transmission along the isolation path.
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Patent Agency Ranking
公开(公告)号：US20220308610A1
公开(公告)日：2022-09-29
申请号：US17211545
申请日：2021-03-24
Applicant: STMicroelectronics International N.V.
Abstract: A method to bypass a voltage regulator of a system on a chip (SOC) comprising powering a first power domain using a voltage regulator; powering a second power domain using the voltage regulator; coupling a third power domain with an external voltage source; raising an external voltage supply from the external voltage source above a threshold level of the voltage regulator; coupling the first second power domains to the external voltage source; turning OFF the voltage regulator of the SOC after coupling the first power domain of the SOC and the second power domain of the SOC to the external voltage source; and powering the first power domain of the SOC, the second power domain of the SOC, and the third power domain of the SOC with the external voltage source, the external voltage source bypassing the voltage regulator.
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公开(公告)号：US20230168699A1
公开(公告)日：2023-06-01
申请号：US17967498
申请日：2022-10-17
Applicant: STMicroelectronics International N.V.
Inventor： Venkata Narayanan Srinivasan , Mayankkumar Hareshbhai Niranjani , Dhulipalla Phaneendra Kumar , Gourav Garg , Sourabh Banzal
Abstract: An electric device includes: a first power domain; a second power domain; a third power domain, where during power-up, the third, the second, and the first power domains are configured to be powered up sequentially, where during standby-exit, the first, the second, and the third power domains are configured to be powered up sequentially; isolation paths that provide controlled signal transmission among the first, the second, and the third power domains, where each isolation path includes an isolation circuit between an input power domain and an output power domain of the isolation path; and a control circuit in the first power domain, where for each isolation path, the control circuit is configured to generate an isolation control signal for the isolation circuit, where the isolation circuit is configured enable or disable signal transmission along the isolation path.
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公开(公告)号：US11550348B2
公开(公告)日：2023-01-10
申请号：US17211545
申请日：2021-03-24
Applicant: STMicroelectronics International N.V.
Abstract: A method to bypass a voltage regulator of a system on a chip (SOC) comprising powering a first power domain using a voltage regulator; powering a second power domain using the voltage regulator; coupling a third power domain with an external voltage source; raising an external voltage supply from the external voltage source above a threshold level of the voltage regulator; coupling the first second power domains to the external voltage source; turning OFF the voltage regulator of the SOC after coupling the first power domain of the SOC and the second power domain of the SOC to the external voltage source; and powering the first power domain of the SOC, the second power domain of the SOC, and the third power domain of the SOC with the external voltage source, the external voltage source bypassing the voltage regulator.
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公开(公告)号：US20240264229A1
公开(公告)日：2024-08-08
申请号：US18165602
申请日：2023-02-07
Applicant: STMicroelectronics International N.V.
IPC: G01R31/317 , H03K19/0175
CPC classification number: G01R31/31721 , H03K19/017509
Abstract: According to an embodiment, a method for testing multiple power-on-resets in a system-on-chip with a multi-power domain architecture operating under a dual power flow mode is provided. The method includes powering up the system-on-chip to full power mode, decoupling a third power domain from a first power domain and a second power domain, monitoring a general purpose input/output (GPIO) pad of the third power domain during a ramping down of a supply of the third power domain, and detecting a logic transition at the GPIO pad of the third power domain corresponding to a trip-point of the power-on-reset of the third power domain.
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公开(公告)号：US11983025B2
公开(公告)日：2024-05-14
申请号：US17967498
申请日：2022-10-17
Applicant: STMicroelectronics International N.V.
Inventor： Venkata Narayanan Srinivasan , Mayankkumar Hareshbhai Niranjani , Dhulipalla Phaneendra Kumar , Gourav Garg , Sourabh Banzal
Abstract: An electric device includes: a first power domain; a second power domain; a third power domain, where during power-up, the third, the second, and the first power domains are configured to be powered up sequentially, where during standby-exit, the first, the second, and the third power domains are configured to be powered up sequentially; isolation paths that provide controlled signal transmission among the first, the second, and the third power domains, where each isolation path includes an isolation circuit between an input power domain and an output power domain of the isolation path; and a control circuit in the first power domain, where for each isolation path, the control circuit is configured to generate an isolation control signal for the isolation circuit, where the isolation circuit is configured enable or disable signal transmission along the isolation path.
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