公开(公告)号：US20250046371A1

公开(公告)日：2025-02-06

申请号：US18790867

申请日：2024-07-31

Applicant: STMicroelectronics International N.V.

Inventor： Marco PASOTTI ,  Riccardo VIGNALI ,  Alessandro CABRINI ,  Riccardo ZURLA

IPC: G11C13/00

Abstract: An in-memory computation device receives an input signal and provides an output signal. The device includes a memory array with memory cells coupled to word lines that receive word line activation signals indicative of the input signal and coupled to bit lines that generate bit line currents; and a digital detector for sampling the bit line current and, in response, providing the output signal. A digital detector includes: a control stage that compares the bit line current with at least one reference current and generates corresponding control signals; a selection stage that generates a total selection current based on the first bit line current and on the control signals; an integration stage that samples the total selection current; and a charge counter stage that generates the output signal on the basis of a sampled first total selection current and the control signals.

公开(公告)号：US20250080118A1

公开(公告)日：2025-03-06

申请号：US18241813

申请日：2023-09-01

Applicant: STMicroelectronics International N.V.

Inventor： Marco PASOTTI ,  Riccardo ZURLA ,  Marcella CARISSIMI ,  Riccardo VIGNALI ,  Alessandro CABRINI

IPC: H03K21/02

Abstract: An in-memory computation circuit includes a memory array with memory cells arranged in a matrix in rows and columns. Groups of memory cells store computational weights for an in-memory compute (IMC) operation that is performed with a first multiply and accumulate (MAC) elaboration to produce a first analog signal and a second MAC elaboration to produce a second analog signal. An analog-to-digital converter circuit operates to: increment a count value in a counter circuit in response to the first analog signal; convert the count value in the counter circuit to a negated count value; and increment the count value in the counter circuit starting from the negated count value in response to the second analog signal.