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公开(公告)号：US20240404569A1
公开(公告)日：2024-12-05
申请号：US18675916
申请日：2024-05-28
Applicant: STMicroelectronics International N.V.
Inventor： Marcella CARISSIMI , Marco PASOTTI , Riccardo ZURLA
Abstract: An in-memory computation (IMC) device is configured to receive input data and provide intermediate output data. A word line activation circuit receives input data and provides corresponding word line activation signals. A memory array includes memory cells in a matrix arrangement coupled to bit lines and to word lines. Each bit line is traversed by a respective bit line current depending on the memory cells connected to the bit line. Selectors each coupled to a respective part of the bit lines are configured to select one of the respective bit lines. A digital detector for each selector is electrically connected, through the respective selector, with the respective bit line selected. The digital detectors sample the respective bit line currents and, in response to the bit line currents, provide the respective intermediate output data.
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Patent Agency Ranking
公开(公告)号：US20250046371A1
公开(公告)日：2025-02-06
申请号：US18790867
申请日：2024-07-31
Applicant: STMicroelectronics International N.V.
Inventor： Marco PASOTTI , Riccardo VIGNALI , Alessandro CABRINI , Riccardo ZURLA
IPC: G11C13/00
Abstract: An in-memory computation device receives an input signal and provides an output signal. The device includes a memory array with memory cells coupled to word lines that receive word line activation signals indicative of the input signal and coupled to bit lines that generate bit line currents; and a digital detector for sampling the bit line current and, in response, providing the output signal. A digital detector includes: a control stage that compares the bit line current with at least one reference current and generates corresponding control signals; a selection stage that generates a total selection current based on the first bit line current and on the control signals; an integration stage that samples the total selection current; and a charge counter stage that generates the output signal on the basis of a sampled first total selection current and the control signals.
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公开(公告)号：US20250080118A1
公开(公告)日：2025-03-06
申请号：US18241813
申请日：2023-09-01
Applicant: STMicroelectronics International N.V.
Inventor： Marco PASOTTI , Riccardo ZURLA , Marcella CARISSIMI , Riccardo VIGNALI , Alessandro CABRINI
IPC: H03K21/02
Abstract: An in-memory computation circuit includes a memory array with memory cells arranged in a matrix in rows and columns. Groups of memory cells store computational weights for an in-memory compute (IMC) operation that is performed with a first multiply and accumulate (MAC) elaboration to produce a first analog signal and a second MAC elaboration to produce a second analog signal. An analog-to-digital converter circuit operates to: increment a count value in a counter circuit in response to the first analog signal; convert the count value in the counter circuit to a negated count value; and increment the count value in the counter circuit starting from the negated count value in response to the second analog signal.
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公开(公告)号：US20250078922A1
公开(公告)日：2025-03-06
申请号：US18241812
申请日：2023-09-01
Applicant: STMicroelectronics International N.V.
Inventor： Marcella CARISSIMI , Marco PASOTTI , Riccardo ZURLA
Abstract: A memory array includes memory cells arranged in a matrix with cell rows coupled to word lines and cell columns coupled to output bit lines. A control circuit maps a first group of memory cells to a first in-memory compute operation producing computation output signals on first output bit lines from a first matrix vector multiplication of a first input vector with a first group of computation weights stored in the first group of memory cells and maps a second group of memory cells to a second in-memory compute operation producing computation output signals on second output bit lines, different from the first output bit lines, from a second matrix vector multiplication of a second input vector, different from the first input vector, with a second group of computation weights stored in the second group of memory cells. The first and second in-memory compute operations are substantially simultaneously executed.
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公开(公告)号：US20240404594A1
公开(公告)日：2024-12-05
申请号：US18731676
申请日：2024-06-03
Applicant: STMicroelectronics International N.V.
Inventor： Marcella CARISSIMI , Marco PASOTTI , Riccardo ZURLA
Abstract: An in-memory computation device performs a multiply-and-accumulate (MAC) operation. A computation array includes groups of memory cells coupled to a bitline, each group storing a computational weight and having a positive cell flowing a positive-cell current and a negative cell flowing a negative-cell current which are a function of a total current and the sign and absolute value of the respective computational weight. A row-activation circuit receives an input signal and provides, for each input value, during an elaboration interval, a positive-activation signal having a positive-activation duration and a negative-activation signal having a negative-activation duration, the durations being a function of an elaboration duration and of the sign and absolute value of the respective input value. A column-elaboration circuit samples bitline current and provides, in response thereto, at least one output signal.
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公开(公告)号：US20240404568A1
公开(公告)日：2024-12-05
申请号：US18731557
申请日：2024-06-03
Applicant: STMicroelectronics International N.V.
Inventor： Riccardo ZURLA , Marco PASOTTI
Abstract: An in-memory computation device performs a multiply-and-accumulate (MAC) operation. A computation array includes groups of memory cells coupled to a bitline, each group storing a computational weight and having a positive cell flowing a positive-cell current and a negative cell flowing a negative-cell current which are a function of a total current and the sign and absolute value of the respective computational weight. A row-activation circuit receives an input signal and provides, for each input value, during an elaboration interval, a positive-activation signal having a positive-activation duration and a negative-activation signal having a negative-activation duration, the durations being a function of an elaboration duration and of the sign and absolute value of the respective input value. A column-elaboration circuit samples bitline current and provides, in response thereto, at least one output signal.
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