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    TESTING OF COMPARATORS WITHIN A MEMORY SAFETY LOGIC CIRCUIT USING A FAULT ENABLE GENERATION CIRCUIT WITHIN THE MEMORY
    1.
    发明申请
    TESTING OF COMPARATORS WITHIN A MEMORY SAFETY LOGIC CIRCUIT USING A FAULT ENABLE GENERATION CIRCUIT WITHIN THE MEMORY 审中-公开

    公开(公告)号：US20200219579A1

    公开(公告)日：2020-07-09

    申请号：US16702744

    申请日：2019-12-04

    Applicant: STMicroelectronics International N.V.

    Inventor： Rohit BHASIN ,  Shishir KUMAR ,  Tanmoy ROY ,  Deepak Kumar BIHANI

    IPC: G11C29/38 ,  G11C29/14

    Abstract: A decoder decodes a memory address and selectively drives a select line (such as a word line or mux line) of a memory. An encoding circuit encodes the data on select lines to generate an encoded address. The encoded address and the memory address are compared by a comparison circuit to generate a test result signal which is indicative of whether the decoder is operating properly. To test the comparison circuit for proper operation, a subset of an MBIST scan routine causes the encoded address to be blocked from the comparison circuit and a force signal to be applied in its place. A test signal from the scan routine and the force signal are then compared by the comparison circuit, with the test result signal generated from the comparison being indicative of whether the comparison circuit itself is operating properly.

    TESTING OF COMPARATORS WITHIN A MEMORY SAFETY LOGIC CIRCUIT USING A FAULT ENABLE GENERATION CIRCUIT WITHIN THE MEMORY
    2.
    发明申请
    TESTING OF COMPARATORS WITHIN A MEMORY SAFETY LOGIC CIRCUIT USING A FAULT ENABLE GENERATION CIRCUIT WITHIN THE MEMORY 有权

    公开(公告)号：US20210225453A1

    公开(公告)日：2021-07-22

    申请号：US17222119

    申请日：2021-04-05

    Applicant: STMicroelectronics International N.V.

    Inventor： Rohit BHASIN ,  Shishir KUMAR ,  Tanmoy ROY ,  Deepak Kumar BIHANI

    IPC: G11C29/38 ,  G11C29/14

    Abstract: A decoder decodes a memory address and selectively drives a select line (such as a word line or mux line) of a memory. An encoding circuit encodes the data on select lines to generate an encoded address. The encoded address and the memory address are compared by a comparison circuit to generate a test result signal which is indicative of whether the decoder is operating properly. To test the comparison circuit for proper operation, a subset of an MBIST scan routine causes the encoded address to be blocked from the comparison circuit and a force signal to be applied in its place. A test signal from the scan routine and the force signal are then compared by the comparison circuit, with the test result signal generated from the comparison being indicative of whether the comparison circuit itself is operating properly.

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