公开(公告)号：US11418200B2

公开(公告)日：2022-08-16

申请号：US17507221

申请日：2021-10-21

Applicant: STMicroelectronics International N.V.

Inventor： Ankit Gupta ,  Sagnik Mukherjee

IPC: H03L7/089 ,  H03L7/087 ,  H03L7/197

Abstract: A PLL circuit includes a fractional-N divider generating a feedback signal, a first phase-frequency detector that compares the feedback signal to a reference signal to generate first up/down control signals that control a charge pump to generate a charge pump output current. A noise cancelation circuit includes a synchronization circuit that generates first and second synchronized feedback signals from the PLL circuit output and the feedback signal, where the first and second synchronized feedback signals are offset by an integer number of cycles of the PLL circuit output. A second phase-frequency detector circuit compares the first and second synchronized feedback clock signals to generate second up/down control signals whose pulse widths differ by the integer number of PLL cycles. A current digital to analog converter circuit is controlled in response to the second up/down control signals to apply noise canceling sourcing and sinking currents to the charge pump output current.

公开(公告)号：US11095297B2

公开(公告)日：2021-08-17

申请号：US16895092

申请日：2020-06-08

Applicant: STMicroelectronics International N.V.

Inventor： Nitin Gupta ,  Sagnik Mukherjee

IPC: H03L7/099 ,  H03L7/093 ,  H03L7/089

Abstract: A voltage controlled oscillator (VCO) circuit generates an output signal having a frequency which is dependent on a control voltage. A current is generated which is itself dependent on an amplitude of the VCO circuit. The generated current accordingly tracks, to an extent, the temperature behavior of the oscillator within the VCO circuit. The oscillator is driven by the sum of the generated current and a control current dependent on the control voltage. The control voltage may, for example, be generated by a phase lock loop (PLL).

公开(公告)号：US11374580B2

公开(公告)日：2022-06-28

申请号：US17381754

申请日：2021-07-21

Applicant: STMicroelectronics International N.V.

Inventor： Sagnik Mukherjee ,  Ankit Gupta

IPC: H03L7/093 ,  H03L7/099

Abstract: A PLL includes a phase-frequency-detector-and-charge-pump-circuit (PFDCPC) receiving a reference signal and divided signal, and generating a charge-pump current. A loop-filter is between output of the PFDCPC and a reference-voltage. A first voltage-to-current converter (V2I1) has low gain, and a second voltage-to-current converter (V2I2) has high gain. A low-gain-path is between outputs of the PFDCPC and V2I1, and a high-gain-path is between the outputs of the PFDCPC and V2I2. A current-controlled-oscillator receives an input signal, and generates an output signal. A loop divider divides the output signal by a divider-value, producing the divided signal. The low-gain-path runs directly from the PFDCPC, through the V2I1, to the input of the current-controlled-oscillator. The high-gain-path runs from the PFDCPC to the loop-filter, from a tap of the loop-filter to a low-pass filter through a current mirror, from a tap of the low-pass filter through the V2I2, to the input of the current-controlled-oscillator.