公开(公告)号：US20030068000A1

公开(公告)日：2003-04-10

申请号：US10247263

申请日：2002-09-18

Applicant: STMicroelectronics Limited

Inventor： Robert Geoffrey Warren

IPC: G06F003/00 ,  H04L007/00

CPC classification number: G01R31/318552 ,  G01R31/31937

Abstract: A system comprising a host, a target and connection means therebetween. The host has means for providing a clock signal, first output means for outputting said clock signal to said target via said connection means and second output means for outputting data to said target via said connection means, said data being clocked out by said clock signal, said target having first input means for receiving said clock signal from said host, second input means for receiving said data from said host and first output means for outputting data to said host via said connection means. The host further comprises input means for receiving said data from said target, and oversampling means for oversampling the received data from the target and controlling the clocking in of said data received from said target in dependence on said oversampling.

Abstract translation: 一种包括主机，目标和它们之间的连接装置的系统。 主机具有用于提供时钟信号的装置，用于经由所述连接装置将所述时钟信号输出到所述目标的第一输出装置和用于经由所述连接装置将数据输出到所述目标的第二输出装置，所述数据由所述时钟信号输出， 所述目标具有用于从所述主机接收所述时钟信号的第一输入装置，用于从所述主机接收所述数据的第二输入装置和用于经由所述连接装置向所述主机输出数据的第一输出装置。 主机还包括用于从所述目标接收所述数据的输入装置，以及过采样装置，用于对来自目标的接收数据进行过采样，并根据所述过采样来控制从所述目标接收的所述数据的时钟。