公开(公告)号：US11955971B2

公开(公告)日：2024-04-09

申请号：US17590668

申请日：2022-02-01

申请人： Rambus Inc.

发明人： Robert E. Palmer ,  Andrew Fuller ,  Hsuan-Jung Su

IPC分类号： G11C7/10 ,  G01R31/3193 ,  G11C11/4076 ,  H03K19/094

CPC分类号： H03K19/09429 ,  G01R31/31937 ,  G11C7/1057 ,  G11C7/1084 ,  G11C11/4076

摘要： An integrated circuit comprises a signal transmitter and a sampling circuit coupled to the signal transmitter, wherein the sampling circuit is to sample output voltage levels of an output of the signal transmitter at different respective times. The integrated circuit further comprises a measurement circuit coupled to the sampling circuit, wherein the measurement circuit is to compare the output voltage levels of the output of the signal transmitter to corresponding reference voltages to identify a first time when a first output voltage level equals a first reference voltage and a second time when a second output voltage level equals a second reference voltage. A time difference between the first time and the second time is used to configure a slew rate adjustment control of the signal transmitter.

公开(公告)号：US20240077533A1

公开(公告)日：2024-03-07

申请号：US18506197

申请日：2023-11-10

申请人： MediaTek Singapore Pte. Ltd.

发明人： Ashish Kumar NAYAK ,  Hugh Thomas MAIR ,  Anshul VARMA ,  Anand RAJAGOPALAN

IPC分类号： G01R31/317 ,  G01R31/30 ,  G01R31/3193 ,  H03K3/03 ,  H03K5/134

CPC分类号： G01R31/31725 ,  G01R31/3016 ,  G01R31/31937 ,  H03K3/0315 ,  H03K5/134

摘要： An integrated circuit includes a programmable delay path comprising a plurality of path delay tuners configured to receive a plurality of control signals and add to the programmable delay path an amount of cell delay and an amount of wire delay that are based on the plurality of control signals. The integrated circuit further includes a controller configured to provide the plurality of control signals to the programmable delay path, receive a signal from the programmable delay path, and compare the signal to a reference signal.

公开(公告)号：US20230417832A1

公开(公告)日：2023-12-28

申请号：US18158181

申请日：2023-01-23

申请人： Samsung Electronics Co., Ltd.

发明人： Kwang Kyu KIM ,  Jae-ll Choi

IPC分类号： G01R31/317 ,  G01R31/3193

CPC分类号： G01R31/31726 ,  G01R31/31937

摘要： Provided is a training method capable of reducing or minimizing a training time. The training method includes, for each of devices to be tested, calculating a first eye width at which a first signal and a second signal synchronize with each other at a first operation speed, and calculating a second eye width at which the first signal and the second signal synchronize with each other at a second operation speed different from the first operation speed; performing machine learning on the first eye width and the second eye width to derive a model showing a relation between operation speeds and eye widths; and calculating a third eye width corresponding to a third operation speed different from the first operation speed and the second operation speed, using the model.

公开(公告)号：US20180299507A1

公开(公告)日：2018-10-18

申请号：US16014117

申请日：2018-06-21

申请人： International Business Machines Corporation

发明人： Pawel Jasionowski

IPC分类号： G01R31/3177 ,  G01R31/3193 ,  G06F17/16 ,  H03K19/00 ,  H03K19/0175 ,  G06N99/00

CPC分类号： G06N10/00 ,  G01R31/31937 ,  G06F17/11 ,  G06F17/16 ,  H03K19/0002 ,  H03K19/017509

摘要： A method and associated systems for using direct sums and invariance groups to optimize the testing of partially symmetric quantum-logic circuits is disclosed. A test system receives information that describes the architecture of a quantum-logic circuit to be tested. The system uses this information to organize the circuit's inputs into two or more mutually exclusive subsets of inputs. The system computes a direct sum of a set of groups associated with the subsets in order to generate an invariance group that contains one or more invariant permutations of the circuit's inputs. These invariant permutations can be used to reduce the number of tests required to fully verify the circuit for all possible input vectors. Once one specific input vector has been verified, there is no need to test other vectors that can be generated by performing any one of the invariant permutations upon the previously verified vector.

公开(公告)号：US10082539B2

公开(公告)日：2018-09-25

申请号：US15194645

申请日：2016-06-28

申请人： International Business Machines Corporation

发明人： Pawel Jasionowski

IPC分类号： G01R31/00 ,  G01R31/3177 ,  G06N99/00 ,  G06F17/16 ,  G06F17/11 ,  H03K19/00 ,  H03K19/0175

CPC分类号： G06N10/00 ,  G01R31/31937 ,  G06F17/11 ,  G06F17/16 ,  H03K19/0002 ,  H03K19/017509

摘要： A method and associated systems for using direct sums and invariance groups to optimize the testing of partially symmetric quantum-logic circuits is disclosed. A test system receives information that describes the architecture of a quantum-logic circuit to be tested. The system uses this information to organize the circuit's inputs into two or more mutually exclusive subsets of inputs. The system computes a direct sum of a set of groups associated with the subsets in order to generate an invariance group that contains one or more invariant permutations of the circuit's inputs. These invariant permutations can be used to reduce the number of tests required to fully verify the circuit for all possible input vectors. Once one specific input vector has been verified, there is no need to test other vectors that can be generated by performing any one of the invariant permutations upon the previously verified vector.

公开(公告)号：US20180246168A1

公开(公告)日：2018-08-30

申请号：US15752825

申请日：2016-08-12

申请人： Novelda AS

发明人： Tor Sverre Lande ,  Håkon André Hjortland

IPC分类号： G01R31/317 ,  G01R31/3193 ,  H03K21/02 ,  H03K21/08 ,  H03K5/14

CPC分类号： G01R31/31725 ,  G01R31/31937 ,  H03K5/14 ,  H03K21/02 ,  H03K21/08 ,  H03K2005/00078

摘要： A delay measurement apparatus for measuring a delay unit comprising: a clock; clock counter; a digital signal source that is uncorrelated with the clock; a first detector arranged to detect transitions of the digital signal entering the delay unit; a first accumulator arranged to accumulate the current clock counter value based on the output of the first detector; a second detector arranged to detect transitions of the digital signal exiting the delay unit; a second accumulator arranged to accumulate the current clock counter value based on the output of the second detector; a measurement counter arranged to count the number of transitions of the digital signal passing through the delay unit; and a calculation device arranged to calculate an average number of clock cycles that elapse while a transition of the digital signal passes through the delay unit based on the first accumulator, the second accumulator and the measurement counter.

公开(公告)号：US09991974B2

公开(公告)日：2018-06-05

申请号：US15453422

申请日：2017-03-08

申请人： Mitsubishi Electric Corporation

发明人： Yoshinori Takahashi

IPC分类号： G01R31/02 ,  H04B17/00 ,  H04B17/16 ,  G01R31/28 ,  G01R31/317

CPC分类号： H04B17/16 ,  G01R31/2822 ,  G01R31/2851 ,  G01R31/317 ,  G01R31/31716 ,  G01R31/31937 ,  H04B17/13

摘要： An integrated circuit according to the present invention includes a transmission circuit that transmits a millimeter wave signal, a detection section that detects the millimeter wave signal, an output terminal connected to an output of the transmission circuit via a first wire, a detection terminal provided adjacent to the output terminal and connected to an input of the detection section via a second wire, a first grounding terminal provided adjacent to the output terminal and connected to the transmission circuit via a first grounding wire for grounding the transmission circuit and a second grounding terminal provided adjacent to the detection terminal and connected to the detection section via a second grounding wire for grounding the detection section, wherein the first grounding wire and the second grounding wire are arranged around the first wire and the second wire.

公开(公告)号：US09952277B2

公开(公告)日：2018-04-24

申请号：US15097291

申请日：2016-04-13

申请人： SYNC-TECH SYSTEM CORP.

发明人： Hung-Wei Lai ,  Tsung-Jun Lee

IPC分类号： G01R31/28 ,  G01R31/3185

CPC分类号： G01R31/2853 ,  G01R31/2844 ,  G01R31/2884 ,  G01R31/318511 ,  G01R31/31937 ,  H01L22/32

摘要： A test device uses a single probe to test plurality of pads of at least one chip, and includes a test circuit, a plurality of short-circuit elements and a plurality of probes. The plurality of short-circuit elements is formed in scribe lines around the at least one chip, where each of the plurality of short-circuit elements connects the plurality of pads, and the plurality of pads includes one testing pad and at least one non-testing pad. The plurality of probes receives a plurality of test signals generated by the at least one chip from the testing pad via the plurality of short-circuit elements, so the test circuit generates a test result according to the plurality of test signals.

公开(公告)号：US20180106864A1

公开(公告)日：2018-04-19

申请号：US15689237

申请日：2017-08-29

申请人： STMicroelectronics (Grenoble 2) SAS

发明人： Nicolas Moeneclaey

IPC分类号： G01R31/3193 ,  G01R31/3187 ,  H04L7/00 ,  H03L7/18 ,  H03L7/085 ,  G01R31/317

CPC分类号： G01R31/31937 ,  G01R31/31718 ,  G01R31/3187 ,  H01L27/14643 ,  H03L7/085 ,  H03L7/18 ,  H03M1/00 ,  H03M1/12 ,  H03M2201/4233 ,  H04L7/0025 ,  H04N3/155 ,  H04N5/335 ,  H04N5/3765 ,  H04N5/378

摘要： A method can be used to generate a reference clock signal having a reference frequency. N clock sub-signals are generated, where N is greater than or equal to 2. The N clock sub-signals are successively mutually shifted out of phase by π/N and each clock sub-signal has an elementary frequency that is equal to the reference frequency divided by N. The N clock sub-signals are propagated over propagation paths. The elementary frequency and a length of the longest propagation path are chosen so that each sub-signal has an acceptable degree of deformation. The duration of each sub-signal edge is longer than quarter of the period of the reference frequency. The reference clock signal is generated by EXCLUSIVE OR combining the propagated clock sub-signals at the end of their respective propagation paths.

公开(公告)号：US09891267B2

公开(公告)日：2018-02-13

申请号：US15181649

申请日：2016-06-14

申请人： FREESCALE SEMICONDUCTOR, INC.

发明人： Nikolas Bradley Sumikawa ,  Chen He

IPC分类号： G01R31/28 ,  G01R31/3177 ,  G01R31/3185 ,  G01R31/26 ,  G01R31/01 ,  G01R31/18 ,  H01L21/66

CPC分类号： G01R31/18 ,  G01R31/01 ,  G01R31/26 ,  G01R31/2894 ,  G01R31/31718 ,  G01R31/318511 ,  G01R31/31937 ,  H01L22/00

摘要： A fault analysis method comprises: receiving fault data from wafer level testing that identifies locations and test results of a plurality of die; applying a kernel transform to the fault data to produce cluster data, where the kernel transform defines a fault impact distribution that defines fault contribution from the failed die to local die within an outer radial boundary of the fault impact distribution. Applying the kernel transform comprises: centering the fault impact distribution at a location of each die that failed wafer level testing, associating each local die that falls within the outer radial boundary with a respective fault contribution value according to the fault impact distribution, and accruing fault contribution values associated with each respective die of the plurality of die to produce a cluster value for the respective die, which correlates to a probability of failure of the respective die at a future time.