公开(公告)号：US20010003540A1

公开(公告)日：2001-06-14

申请号：US09727300

申请日：2000-11-30

Applicant: STMicroelectronics S.A.

Inventor： Alain Pomet ,  Bernard Plessier ,  Laurent Sourgen

IPC: H04L009/12 ,  H04L009/16 ,  H04L012/22

CPC classification number: H04L9/0891 ,  H04L9/0631 ,  H04L2209/04

Abstract: In an electronic component including a two-way bus through which data elements travel between peripherals and a central processing unit at the rate of a clock signal, the central processing unit and at least one of the peripherals each includes a data encryption/decryption cell. Each data encryption/decryption cell uses the same secret key. The secret key is produced locally at each clock cycle in each cell from a random signal synchronous with the clock signal, and is applied to each of the cells by a one-way transmission line.

Abstract translation: 在包括双向总线的电子部件中，数据元件通过该双向总线以时钟信号的速率在外围设备和中央处理单元之间行进，中央处理单元和至少一个外围设备都包括数据加密/解密单元。 每个数据加密/解密单元使用相同的秘密密钥。 秘密密钥是从与时钟信号同步的随机信号在每个小区中的每个时钟周期本地产生的，并且通过单向传输线应用于每个小区。

公开(公告)号：US20010020857A1

公开(公告)日：2001-09-13

申请号：US09771364

申请日：2001-01-26

Applicant: STMicroelectronics S.A.

Inventor： Alexandre Malherbe ,  Fabrice Marinet ,  Alain Pomet

IPC: H03K005/01

CPC classification number: G06K19/07 ,  G06F13/426

Abstract: A device for the regeneration of a clock signal from an external serial bus includes a ring oscillator and counter. The ring oscillator provides n phases of a clock signal. Of these n phases, one phase is used as a reference and is applied to the counter. It is thus possible to count the number of entire reference clock signal periods between a first pulse and a second pulse received from the bus. In reading the state of the phases in the oscillator upon reception of the second pulse, a determination is made for a current phase corresponding to the phase delay between the reference clock signal and the second pulse of the bus. By using a regeneration device that also includes a ring oscillator and a counter, it is possible to regenerate the clock signal of the bus with high precision.

Abstract translation: 用于从外部串行总线再生时钟信号的装置包括环形振荡器和计数器。 环形振荡器提供时钟信号的n个相位。 在这n个阶段中，使用一个相作为参考，并将其应用于计数器。 因此，可以对从总线接收的第一脉冲和第二脉冲之间的整个参考时钟信号周期的数量进行计数。 在接收到第二脉冲时读取振荡器中的相位状态，确定与基准时钟信号和总线的第二脉冲之间的相位延迟相对应的电流相位。 通过使用还包括环形振荡器和计数器的再生装置，可以高精度地重新生成总线的时钟信号。

公开(公告)号：US20010011914A1

公开(公告)日：2001-08-09

申请号：US09765501

申请日：2001-01-18

Applicant: STMicroelectronics S.A.

Inventor： Alain Pomet

IPC: H03K005/01

CPC classification number: G06F13/426

Abstract: A device for the regeneration of a clock signal uses a reference clock signal given by an internal oscillator to measure the number of reference clock pulses between the first two synchronization pulses sent by an external serial bus or USB at the beginning of each transaction. Thus a rough measurement N is obtained of the USB clock signal to be regenerated. The delay of each of these two synchronization pulses with respect to the previous pulse of the reference clock signal is measured. This delay is computed with respect to an internally defined time unit. On the basis of the measurement of these two delays, and the measurement of the number of reference clock periods, and knowing the measurement n of the period of the reference clock signal in the time unit, the period of the USB clock signal to be regenerated is computed with precision.

Abstract translation: 用于再生时钟信号的装置使用由内部振荡器给出的参考时钟信号来测量在每个事务开始时由外部串行总线或USB发送的前两个同步脉冲之间的参考时钟脉冲的数量。 因此，获得要再生的USB时钟信号的粗略测量N. 测量这两个同步脉冲中相对于参考时钟信号的先前脉冲的延迟。 相对于内部定义的时间单位计算该延迟。 基于这两个延迟的测量和参考时钟周期的数量的测量，并且知道时间单位中的参考时钟信号的周期的测量n，将要再生的USB时钟信号的周期 是精确计算的。

公开(公告)号：US20010004220A1

公开(公告)日：2001-06-21

申请号：US09740269

申请日：2000-12-19

Applicant: STMicroelectronics S.A.

Inventor： Alain Pomet

IPC: H03K003/3562

CPC classification number: G06K19/073 ,  H03K3/0372 ,  H03K3/35625

Abstract: A master-slave D type flip-flop circuit includes a power consumption circuit including a reference stage in parallel with a master and a slave stage of the flip-flop circuit. This structure advantageously provides a switching of the flip-flop circuit on each of the leading and trailing edges of the clock signal for the sequencing of the flip-flop circuit.

Abstract translation: 主从D型触发器电路包括功率消耗电路，其包括与主触发器电路并联的参考级和触发器电路的从动级。 该结构有利地提供触发器电路在时钟信号的前沿和后沿的每一个上的切换，用于触发器电路的排序。