公开(公告)号：US20020126548A1

公开(公告)日：2002-09-12

申请号：US10044307

申请日：2001-10-26

Applicant: STMicroelectronics S.A.

Inventor： Jerome Ciavatti

IPC: H01L021/8242

CPC classification number: H01L21/76897 ,  H01L27/10888 ,  Y10S438/954

Abstract: A method for manufacturing a DRAM cell including two active word lines having a drain region and distinct source regions, including, after the forming of insulated conductive lines, the steps of: depositing a first, then a second selectively etchable insulating layers; etching the second insulating layer to only maintain it above conductive lines; depositing and leveling a third insulating layer selectively etchable with respect to at least the second insulating layer; opening the first and third insulating layers to expose the drain region and an insulating trench; filling the previously-formed opening with a conductive material; polishing the entire structure; and depositing a fourth insulating layer, selectively etchable with respect to the third insulating layer.

Abstract translation: 一种用于制造DRAM单元的方法，所述DRAM单元包括具有漏极区和不同源极区的两个有源字线，包括在形成绝缘导线之后的步骤：沉积第一，然后第二可选择蚀刻的绝缘层; 蚀刻第二绝缘层以仅将其保持在导电线之上; 沉积和调平相对于至少第二绝缘层可选择性蚀刻的第三绝缘层; 打开第一和第三绝缘层以暴露漏极区域和绝缘沟槽; 用导电材料填充先前形成的开口; 抛光整个结构; 以及沉积相对于所述第三绝缘层可选择性蚀刻的第四绝缘层。