公开(公告)号：US08809141B2

公开(公告)日：2014-08-19

申请号：US11670192

申请日：2007-02-01

申请人： Haowen Bu ,  Rajesh Khamankar ,  Douglas T. Grider

发明人： Haowen Bu ,  Rajesh Khamankar ,  Douglas T. Grider

IPC分类号： H01L29/739

CPC分类号： H01L29/7842 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/78 ,  H01L29/7843 ,  Y10S438/954

摘要： A silicon nitrate layer (110) is formed over a transistor gate (40) and source and drain regions (70). The as-formed silicon nitride layer (110) comprises a first tensile stress and a high hydrogen concentration. The as-formed silicon nitride layer (110) is thermally annealed converting the first tensile stress into a second tensile stress that is larger than the first tensile stress. Following the thermal anneal, the hydrogen concentration in the silicon nitride layer (110) is greater than 12 atomic percent.

摘要翻译： 在晶体管栅极（40）和源极和漏极区域（70）之上形成硝酸氧化物层（110）。 所形成的氮化硅层（110）包括第一拉伸应力和高氢浓度。 将所形成的氮化硅层（110）进行热退火，将第一拉伸应力转换成大于第一拉伸应力的第二拉伸应力。 在热退火之后，氮化硅层（110）中的氢浓度大于12原子％。

公开(公告)号：US20120164804A1

公开(公告)日：2012-06-28

申请号：US13409832

申请日：2012-03-01

申请人： Arup Bhattacharyya

发明人： Arup Bhattacharyya

IPC分类号： H01L21/336

CPC分类号： H01L29/513 ,  B82Y10/00 ,  H01L29/42332 ,  H01L29/7881 ,  H01L29/792 ,  Y10S438/954

摘要： Methods of forming non-volatile memory cell structures are described that facilitate the use of band-gap engineered gate stacks with asymmetric tunnel barriers in reverse and normal mode floating node memory cells that allow for direct tunnel programming and erase, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention. The low voltage direct tunneling program and erase capability reduces damage to the gate stack and the crystal lattice from high energy carriers, reducing write fatigue and enhancing device lifespan. The low voltage direct tunnel program and erase capability also enables size reduction through low voltage design and further device feature scaling. Such memory cells also allow multiple bit storage. These characteristics allow such memory cells to operate within the definition of a universal memory, capable of replacing both DRAM and ROM in a system.

摘要翻译： 描述了形成非易失性存储单元结构的方法，其有助于在反向和正常模式浮动节点存储器单元中使用具有不对称隧道势垒的带隙工程化栅极堆叠，这允许直接隧道编程和擦除，同时保持高电荷阻挡屏障 和深载体捕获位点保持良好的电荷。 低电压直接隧道编程和擦除能力降低了高能量载流子对栅极堆叠和晶格的损害，减少了写入疲劳和增强了器件寿命。 低电压直接隧道编程和擦除功能还可以通过低电压设计和进一步的器件特性缩放来缩小尺寸。 这样的存储器单元还允许多个位存储。 这些特性允许这样的存储器单元在通用存储器的定义内操作，能够替换系统中的DRAM和ROM。

公开(公告)号：US07947607B2

公开(公告)日：2011-05-24

申请号：US12342837

申请日：2008-12-23

申请人： Chao-I Wu

发明人： Chao-I Wu

IPC分类号： H01L21/311

CPC分类号： G11C16/16 ,  G11C16/0466 ,  G11C16/12 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11568 ,  Y10S438/954

摘要： A virtual ground array structure uses inversion bit lines in order to eliminate the need for implanted bit lines. As a result, the cell size can be reduced, which can provide greater densities and smaller packaging.

摘要翻译： 虚拟接地阵列结构使用反转位线，以消除对注入位线的需要。 结果，可以减小电池尺寸，这可以提供更大的密度和更小的封装。

公开(公告)号：US07799638B2

公开(公告)日：2010-09-21

申请号：US12263091

申请日：2008-10-31

申请人： I-Chen Yang ,  Yao-Wen Chang ,  Tao-Cheng Lu

发明人： I-Chen Yang ,  Yao-Wen Chang ,  Tao-Cheng Lu

IPC分类号： H01L21/00

CPC分类号： H01L21/28282 ,  H01L27/11568 ,  H01L29/4234 ,  Y10S438/954

摘要： The invention is directed to a method for forming a memory array. The method comprises steps of providing a substrate having a charge trapping structure formed thereon. A patterned material layer is formed over the substrate and the patterned material layer having a plurality of trenches expose a portion of the charge trapping structure. Furthermore, a plurality of conductive spacers are formed on the sidewalls of the trenches of the patterned material layer respectively and a portion of the charge trapping structure at the bottom of the trenches is exposed by the conductive spacers. An insulating layer is formed over the substrate to fill up the trenches of the patterned material layer. Moreover, a planarization process is performed to remove a portion of the insulating layer until a top surface of the patterned material layer and a top surface of each of the conductive spacers are exposed.

摘要翻译： 本发明涉及一种用于形成存储器阵列的方法。 该方法包括提供其上形成有电荷捕获结构的衬底的步骤。 图案化的材料层形成在衬底上，并且具有多个沟槽的图案化材料层暴露电荷俘获结构的一部分。 此外，在图案化材料层的沟槽的侧壁上分别形成多个导电间隔物，并且沟槽底部的电荷捕获结构的一部分被导电间隔物暴露。 在衬底上形成绝缘层以填充图案化材料层的沟槽。 此外，执行平面化处理以去除绝缘层的一部分，直到图案化材料层的顶表面和每个导电间隔物的顶表面露出。

公开(公告)号：US20090315100A1

公开(公告)日：2009-12-24

申请号：US12478328

申请日：2009-06-04

申请人： Hee-Don Jeong

发明人： Hee-Don Jeong

IPC分类号： H01L29/792 ,  H01L21/28 ,  H01L21/336

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/4234 ,  Y10S438/954

摘要： Disclosed is a method of manufacturing a semiconductor device. The method includes forming an oxide-nitride-oxide (ONO) layer over a semiconductor substrate, and forming a recess over the semiconductor substrate by etching the ONO layer, forming a vertical structure pattern being higher than the ONO layer over the recess, sequentially forming a spacer oxide film and a first gate poly over the side wall of the vertical structure pattern, and forming a nitride film spacer at a partial region of the side wall of the first gate poly, removing the nitride film spacer, and forming a second gate poly in a spacer shape over the side wall of the first gate poly, and forming a first split gate and a second split gate, symmetrically divided from each other, by removing the vertical structure pattern.

摘要翻译： 公开了半导体器件的制造方法。 该方法包括在半导体衬底上形成氧化物 - 氧化物（ONO）层，并通过蚀刻ONO层在半导体衬底上形成凹陷，在凹槽上形成高于ONO层的垂直结构图案，依次形成 间隔氧化物膜和在垂直结构图案的侧壁上的第一栅极聚合物，并且在第一栅极聚合物的侧壁的部分区域处形成氮化物膜间隔物，去除氮化物膜间隔物，并形成第二栅极 在第一栅极多晶硅的侧壁上形成间隔物形状的多晶硅，并且通过去除垂直结构图案形成对称分割的第一分离栅极和第二分离栅极。

公开(公告)号：US07612403B2

公开(公告)日：2009-11-03

申请号：US11131006

申请日：2005-05-17

申请人： Arup Bhattacharyya

发明人： Arup Bhattacharyya

IPC分类号： H01L29/788

CPC分类号： H01L29/513 ,  B82Y10/00 ,  H01L29/42332 ,  H01L29/7881 ,  H01L29/792 ,  Y10S438/954

摘要： Non-volatile memory devices and arrays are described that facilitate the use of band-gap engineered gate stacks with asymmetric tunnel barriers in reverse and normal mode floating node memory cells in NOR or NAND memory architectures that allow for direct tunnel programming and erase, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention. The low voltage direct tunneling program and erase capability reduces damage to the gate stack and the crystal lattice from high energy carriers, reducing write fatigue and enhancing device lifespan. The low voltage direct tunnel program and erase capability also enables size reduction through low voltage design and further device feature scaling. Memory cells of the present invention also allow multiple bit storage. These characteristics allow memory device embodiments of the present invention to operate within the definition of a universal memory, capable of replacing both DRAM and ROM in a system.

摘要翻译： 描述了非易失性存储器件和阵列，其有助于在NOR或NAND存储器架构中的反向和正常模式浮动节点存储器单元中使用具有非对称隧道势垒的带隙工程化栅极堆叠，这允许直接隧道编程和擦除，同时保持 高电荷阻挡屏障和深载体捕获位点，具有良好的电荷保留性。 低电压直接隧道编程和擦除能力降低了高能量载流子对栅极堆叠和晶格的损害，减少了写入疲劳和增强了器件寿命。 低电压直接隧道编程和擦除功能还可以通过低电压设计和进一步的器件特性缩放来缩小尺寸。 本发明的存储单元还允许多位存储。 这些特征允许本发明的存储器件实施例在通用存储器的定义内操作，能够替代系统中的DRAM和ROM。

公开(公告)号：US07537998B2

公开(公告)日：2009-05-26

申请号：US11782073

申请日：2007-07-24

申请人： Joon Hyeon Lee ,  Woon Yong Kim

发明人： Joon Hyeon Lee ,  Woon Yong Kim

IPC分类号： H01L21/336

CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823462 ,  H01L29/6656 ,  Y10S438/954 ,  Y10S438/981

摘要： Forming salicide in a semiconductor device includes the steps of: forming a first and a second gate oxide film and in a non-salicide region and a salicide region, the first gate oxide film being thicker than the second gate oxide film; forming a conductive layer and a nitride based hard mask layer, and then selectively removing the conductive layer, the hard mask layer, the first gate oxide film, and the second gate oxide film, thereby forming gate electrodes and simultaneously exposing an active region of the salicide region; forming a spacer oxide film on an upper surface, except for the hard mask layer, of a second resultant structure; selectively removing the spacer oxide film, thereby forming a spacer and simultaneously exposing the active region of the salicide region; removing the hard mask layer; and forming a salicide film on the upper surfaces of the gate electrodes and on the surface of the active region in the salicide region. Therefore, a non-salicide region and a salicide region can be formed selectively and simultaneously in a one-chip semiconductor device, so that the number of steps for a salicide forming process can be reduced.

摘要翻译： 在半导体器件中形成硅化物包括以下步骤：形成第一和第二栅极氧化物膜，并且在非自对准硅化物区域和自对准硅化物区域中，所述第一栅极氧化物膜比所述第二栅极氧化物膜厚; 形成导电层和氮化物基硬掩模层，然后选择性地去除导电层，硬掩模层，第一栅极氧化膜和第二栅极氧化物膜，由此形成栅电极并同时曝光 自杀地区; 在除了硬掩模层之外的上表面上形成第二结构结构的间隔氧化膜; 选择性地去除间隔氧化膜，从而形成间隔物并同时暴露自对准区域的活性区域; 去除硬掩模层; 以及在所述栅电极的上表面和所述自对准区域中的有源区的表面上形成自对准硅膜。 因此，可以在单芯片半导体器件中选择性和同时地形成非自对准硅化物区域和自对准硅化物区域，从而可以减少用于硅化物形成工艺的步骤数量。

公开(公告)号：US20090103363A1

公开(公告)日：2009-04-23

申请号：US12342837

申请日：2008-12-23

申请人： Chao-I Wu

发明人： Chao-I Wu

IPC分类号： G11C16/06 ,  H01L21/8239

CPC分类号： G11C16/16 ,  G11C16/0466 ,  G11C16/12 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11568 ,  Y10S438/954

摘要： A virtual ground array structure uses inversion bit lines in order to eliminate the need for implanted bit lines. As a result, the cell size can be reduced, which can provide greater densities and smaller packaging.

摘要翻译： 虚拟接地阵列结构使用反转位线，以消除对注入位线的需要。 结果，可以减小电池尺寸，这可以提供更大的密度和更小的封装。

公开(公告)号：US07486560B2

公开(公告)日：2009-02-03

申请号：US11424748

申请日：2006-06-16

申请人： Chao-I Wu

发明人： Chao-I Wu

IPC分类号： G11C11/34 ,  G11C16/04 ,  H01L29/76

CPC分类号： G11C16/16 ,  G11C16/0466 ,  G11C16/12 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11568 ,  Y10S438/954

摘要： A virtual ground array structure uses inversion bit lines in order to eliminate the need for implanted bit lines. As a result, the cell size can be reduced, which can provide greater densities and smaller packaging.

摘要翻译： 虚拟接地阵列结构使用反转位线，以消除对注入位线的需要。 结果，可以减小电池尺寸，这可以提供更大的密度和更小的封装。

公开(公告)号：US07482623B2

公开(公告)日：2009-01-27

申请号：US11085460

申请日：2005-03-21

申请人： Takao Nishikawa ,  Yoshihiro Iwasa ,  Shin-ichiro Kobayashi ,  Taishi Takenobu

发明人： Takao Nishikawa ,  Yoshihiro Iwasa ,  Shin-ichiro Kobayashi ,  Taishi Takenobu

IPC分类号： H01L29/08 ,  H01L35/24 ,  H01L51/00 ,  H01L21/00 ,  H01L51/40 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L51/0533 ,  B82Y10/00 ,  H01L27/283 ,  H01L51/002 ,  H01L51/0046 ,  H01L51/0545 ,  Y10S438/954 ,  Y10S438/981

摘要： An organic semiconductor device includes a substrate, a gate electrode formed directly on the substrate , gate insulating film formed directly on the gate electrode, a source electrode and a drain electrode formed directly on the gate insulating film, an organic semiconductor layer formed directly on the source electrode and the drain electrode, and a voltage control layer disposed directly between the gate insulating film and the organic semiconductor layer and directly contacting the source electrode and the drain electrode, wherein the voltage control layer gives an ambipolar characteristic to the organic semiconductor layer.

摘要翻译： 有机半导体器件包括基板，直接形成在基板上的栅极电极，直接形成在栅电极上的栅极绝缘膜，直接形成在栅极绝缘膜上的源电极和漏电极，直接形成在栅绝缘膜上的有机半导体层 源极电极和漏电极，以及电压控制层，其直接设置在栅极绝缘膜和有机半导体层之间并且直接接触源电极和漏电极，其中电压控制层给有机半导体层提供双极特性。