公开(公告)号：US20020015346A1

公开(公告)日：2002-02-07

申请号：US09879799

申请日：2001-06-12

Applicant: STMicroelectronics S.A.

Inventor： Francois Jacquet ,  Olivier Godcheau

IPC: G11C007/14

CPC classification number: G11C7/14 ,  G11C7/12 ,  G11C11/4094 ,  G11C11/4099

Abstract: A method is for controlling reading of a dynamic random access memory (DRAM) including memory cells connected to a bit line of a memory plane of the DRAM and associated with a main reference cell connected to a reference bit line. The method may include reading and refreshing the contents of the memory cell and pre-charging the bit line, the reference bit line and the main reference cell for a subsequent read access. During reading and refreshing the memory cell, the main reference cell and a secondary reference cell connected to the bit line may be activated and, after having deactivated the two reference cells, they are pre-charged to a final pre-charge voltage. The final pre-charge voltage may be chosen to be less than or greater than (as a function of the NMOS or PMOS technology used, respectively) half the sum of a high-state storage voltage and a low-state storage voltage.

Abstract translation: 一种用于控制动态随机存取存储器（DRAM）的读取的方法，所述动态随机存取存储器（DRAM）包括连接到DRAM的存储器平面的位线并与连接到参考位线的主参考单元相关联的存储器单元。 该方法可以包括读取和刷新存储器单元的内容并对位线预先充电，参考位线和主参考单元用于随后的读取访问。 在读取和刷新存储器单元期间，主参考单元和连接到位线的次参考单元可以被激活，并且在使两个参考单元停用之后，它们被预充电到最终的预充电电压。 最终的预充电电压可以被选择为小于或大于（作为分别使用的NMOS或PMOS技术的函数）作为高状态存储电压和低状态存储电压之和的一半。