公开(公告)号：US20040044943A1

公开(公告)日：2004-03-04

申请号：US10453844

申请日：2003-06-03

Applicant: STMICROELECTRONICS S.A.

Inventor： Francois Jacquet ,  Jean-Pierre Schoellkopf

IPC: G11C029/00

CPC classification number: G06F11/1008 ,  G06F11/1048

Abstract: A memory circuit with an error correcting system comprising an address bus (102), an input data bus (108), and an output data bus (115), the circuit comprising a memory having an address bus (113), a data bus (114) and an error correcting circuit comprising an encoder (107). A first address register (104) is connected to the input address bus of the circuit for successively storing addresses corresponding to memory write operations only. A second data register (105) is connected to the input data bus of the circuit (108) for storing data transmitted to the encoder (107). Circuits make it possible to introduce a one-cycle shift into the memory writes, without modifying reads, giving the encoder more time to compute error correcting codes.

Abstract translation: 一种具有包括地址总线（102），输入数据总线（108）和输出数据总线（115）的纠错系统的存储器电路，该电路包括具有地址总线（113），数据总线 114）和包括编码器（107）的纠错电路。 第一地址寄存器（104）连接到电路的输入地址总线，用于仅依次存储对应于存储器写入操作的地址。 第二数据寄存器（105）连接到电路（108）的输入数据总线，用于存储发送到编码器（107）的数据。 电路使得可以在存储器写入中引入一个周期的移位，而不修改读取，给编码器更多的时间来计算纠错码。

公开(公告)号：US20020015346A1

公开(公告)日：2002-02-07

申请号：US09879799

申请日：2001-06-12

Applicant: STMicroelectronics S.A.

Inventor： Francois Jacquet ,  Olivier Godcheau

IPC: G11C007/14

CPC classification number: G11C7/14 ,  G11C7/12 ,  G11C11/4094 ,  G11C11/4099

Abstract: A method is for controlling reading of a dynamic random access memory (DRAM) including memory cells connected to a bit line of a memory plane of the DRAM and associated with a main reference cell connected to a reference bit line. The method may include reading and refreshing the contents of the memory cell and pre-charging the bit line, the reference bit line and the main reference cell for a subsequent read access. During reading and refreshing the memory cell, the main reference cell and a secondary reference cell connected to the bit line may be activated and, after having deactivated the two reference cells, they are pre-charged to a final pre-charge voltage. The final pre-charge voltage may be chosen to be less than or greater than (as a function of the NMOS or PMOS technology used, respectively) half the sum of a high-state storage voltage and a low-state storage voltage.

Abstract translation: 一种用于控制动态随机存取存储器（DRAM）的读取的方法，所述动态随机存取存储器（DRAM）包括连接到DRAM的存储器平面的位线并与连接到参考位线的主参考单元相关联的存储器单元。 该方法可以包括读取和刷新存储器单元的内容并对位线预先充电，参考位线和主参考单元用于随后的读取访问。 在读取和刷新存储器单元期间，主参考单元和连接到位线的次参考单元可以被激活，并且在使两个参考单元停用之后，它们被预充电到最终的预充电电压。 最终的预充电电压可以被选择为小于或大于（作为分别使用的NMOS或PMOS技术的函数）作为高状态存储电压和低状态存储电压之和的一半。

公开(公告)号：US20040252554A1

公开(公告)日：2004-12-16

申请号：US10726263

申请日：2003-12-02

Applicant: STMicroelectronics S.A.

Inventor： Richard Fournel ,  Emmanuel Vincent ,  Sylvie Bruyere ,  Philippe Candelier ,  Francois Jacquet

IPC: G11C016/04

CPC classification number: G11C14/00 ,  G11C17/14

Abstract: An SRAM memory cell includes first and second inverters (14, 16) interconnected between first and second data nodes. Each inverter is formed from complementary MOS transistors (18, 20, 18null, 20null) connected in series between a DC voltage supply source and a grounding circuit (22). A circuit (28, 30) programs the MOS transistors by causing an irreversible degradation of a gate oxide layer of at least some of the transistors (18, 18null).

Abstract translation: SRAM存储单元包括在第一和第二数据节点之间互连的第一和第二反相器（14,16）。 每个反相器由串联连接在DC电压源和接地电路（22）之间的互补MOS晶体管（18,20,18'，20'）形成。 电路（28,30）通过使至少一些晶体管（18,18'）的栅极氧化层不可逆地退化来对MOS晶体管进行编程。

公开(公告)号：US20040246800A1

公开(公告)日：2004-12-09

申请号：US10860080

申请日：2004-06-03

Applicant: STMicroelectronics S.A.

Inventor： Franck Genevaux ,  Francois Jacquet

IPC: G11C007/00

CPC classification number: G11C7/12 ,  G11C7/065 ,  G11C2207/065

Abstract: A sense amplifier connected to first and second bit lines, comprising means for precharging said bit lines to a high voltage, means for connecting one or the other of the bit lines to a memory cell, said connection causing according to the state of the memory cell a maintaining of the bit line at the high voltage or a voltage reduction, first and second transistors respectively controlled by the first and second bit lines, and, in series with the first and second transistors, a controllable means for the current through the transistor controlled by the bit line connected to the memory cell to be greater than the current through the other transistor when the voltages of the two bit lines are at the high voltage.

Abstract translation: 连接到第一和第二位线的感测放大器包括用于将所述位线预充电到高电压的装置，用于将一个或另一个位线连接到存储器单元的装置，所述连接根据存储器单元的状态 分别由第一和第二位线控制的高电压或电压降低的位线的保持，以及与第一和第二晶体管串联的用于通过晶体管控制的电流的可控制装置 当两个位线的电压处于高电压时，连接到存储单元的位线大于通过另一个晶体管的电流。

公开(公告)号：US20020159321A1

公开(公告)日：2002-10-31

申请号：US10135981

申请日：2002-04-29

Applicant: STMicroelectronics S.A.

Inventor： Francois Jacquet ,  Florent Vautrin

IPC: G11C007/00

CPC classification number: G11C7/062 ,  G11C7/14 ,  G11C11/406 ,  G11C11/4091

Abstract: A device for reading from a capacitive memory cell, including a comparator of the voltage stored in the memory cell with respect to a reference value, which exhibits a high input impedance; a refreshment means distinct from the comparator, the refreshment means having a low output impedance and being controlled by the comparator to impose a refreshment voltage to the memory cell; and means for controllably connecting the refreshment means to the memory cell.

Abstract translation: 一种用于从电容存储单元读取的装置，包括相对于参考值存储在存储单元中的电压的比较器，该比较器具有高输入阻抗; 与比较器不同的刷新装置，刷新装置具有低输出阻抗并由比较器控制以向存储器单元施加刷新电压; 以及用于将所述刷新装置可控地连接到所述存储单元的装置。