公开(公告)号：US20020184420A1

公开(公告)日：2002-12-05

申请号：US10115888

申请日：2002-04-03

Applicant: STMicroelectronics S.r.I.

Inventor： Alessandro Francesco Maone ,  Maurizio Francesco Perroni

IPC: G06F013/42

CPC classification number: G06F13/4239

Abstract: An interface manages the exchange of information between a bus system and a memory during reading, according to a communication protocol. The interface has a protocol-decoding unit, which receives from outside commands and information for managing the reading and generates a wait-code enabling signal, and a wait-state generating unit, which is connected to the protocol-decoding unit and outputs wait codes upon receipt of the wait-code enabling signal. When the memory ends reading, as signaled by switching of a read-state signal, a wait-state disabling circuit generates and supplies an end-of-waiting control signal to the wait-state generating unit, which thus outputs an end-of-waiting code.

Abstract translation: 根据通信协议，接口在读取期间管理总线系统和存储器之间的信息交换。 该接口具有从外部指令接收的协议解码单元和用于管理读取的信息并产生等待代码使能信号，以及等待状态生成单元，其连接到协议解码单元并输出等待代码 在接收到等待代码使能信号时。 当存储器结束读取时，如通过切换读取状态信号所指示的，等待状态禁止电路产生并将等待结束的控制信号提供给等待状态产生单元，从而输出结束等待状态， 等待代码。

公开(公告)号：US20020145909A1

公开(公告)日：2002-10-10

申请号：US10077687

申请日：2002-02-15

Applicant: STMicroelectronics S.r.I.

Inventor： Alessandro Francesco Maone ,  Maurizio Francesco Perroni

IPC: G11C011/34

CPC classification number: G11C16/32 ,  G11C16/26

Abstract: The reading timing device has a data-sensing stage, receiving a sensing-latch signal, and an output stage, including an output buffer and enabled at a first switching edge of a synchronization signal. A reading timing stage generates the sensing-latch signal not before a preset time interval from the first switching edge of the synchronization signal. Thereby, reading, in particular data-latching in the data-sensing stage, is temporarily separated from switching of the output buffers. This separation is obtained using the sync signal. Since the output buffers must switch in a preset time from the rising edge of the sync signal, the pulse of the sensing-latch signal is shifted after this time, and more precisely after the falling edge of the sync signal.

Abstract translation: 读取定时装置具有数据感测级，接收感测锁存信号，以及输出级，包括输出缓冲器，并在同步信号的第一开关边沿使能。 读取定时阶段不是在从同步信号的第一切换边缘的预设时间间隔之前产生感测锁存信号。 因此，读取，特别是数据传感级中的数据锁存，暂时与输出缓冲器的切换分开。 使用同步信号获得该分离。 由于输出缓冲器必须在同步信号的上升沿的预设时间内切换，所以在此时间之后，更精确地在同步信号的下降沿之后移动感测锁存信号的脉冲。