公开(公告)号：US20030067036A1

公开(公告)日：2003-04-10

申请号：US10237553

申请日：2002-09-09

Applicant: STMicroelectronics S.r.I.

Inventor： Riccardo Depetro ,  Anna Ponza ,  Antonio Gallerano

IPC: H01L021/336 ,  H01L029/76 ,  H01L029/94 ,  H01L031/062 ,  H01L031/119 ,  H01L031/113

CPC classification number: H01L29/7816 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/4238

Abstract: An MOS electronic device is formed to reduce drain/gate capacity and to increase cutoff frequency. The device includes a field insulating layer that covers a drain region, delimits an active area with an opening, houses a body region in the active area, and houses a source region in the body region. A portion of the body region between drain and source regions forms a channel region. A polycrystalline silicon structure extends along the edge of the opening, partially on the field insulating and active layers. The polycrystalline silicon structure includes a gate region extending along a first portion of the edge on the channel region and partially surrounding the source region and a non-operative region extending along a second portion of the edge, electrically insulated and at a distance from the gate region.

Abstract translation: 形成MOS电子器件以减少漏极/栅极容量并增加截止频率。 该器件包括覆盖漏极区域的场绝缘层，限定具有开口的有源区域，在有源区域中容纳主体区域，并且容纳主体区域中的源极区域。 漏极和源极区域之间的体区的一部分形成沟道区。 多晶硅结构沿着开口的边缘延伸，部分地在场绝缘层和有源层上延伸。 多晶硅结构包括沿沟道区域上的边缘的第一部分延伸并且部分地围绕源极区域的栅极区域和沿边缘的第二部分延伸的非操作区域，电绝缘并且距离栅极一定距离 地区。