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公开(公告)号:US20240355888A1
公开(公告)日:2024-10-24
申请号:US18683523
申请日:2022-11-11
发明人: Masaki SHIRAISHI , Daisuke KAWASE , Tetsuo ODA , Tomoyasu FURUKAWA , Yutaka KATO , Tsubasa MORITSUKA
IPC分类号: H01L29/40 , H01L29/06 , H02M7/5387
CPC分类号: H01L29/402 , H01L29/0623 , H02M7/5387
摘要: The present invention provides: a semiconductor device which has higher resistance to bias at high temperatures and high humidities than ever before, while achieving good connection between a field limiting layer and a field plate; and a power conversion device which uses this semiconductor device. A semiconductor device according to the present invention is characterized by comprising a floating field limiting layer that is provided in a termination region and a field plate that is electrically connected to the field limiting layer, and is also characterized in that: the field plate is formed of a polysilicon; the field plate and the field limiting layer are connected to each other via an Al electrode; and the connection between the field limiting layer and the Al electrode and the connection between the field plate and the Al electrode are established at different contacts.
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公开(公告)号:US20240347628A1
公开(公告)日:2024-10-17
申请号:US18298815
申请日:2023-04-11
申请人: NXP USA, Inc.
发明人: Jie Hu
IPC分类号: H01L29/778 , H01L29/40 , H01L29/66
CPC分类号: H01L29/7786 , H01L29/402 , H01L29/66462
摘要: A semiconductor device includes a semiconductor substrate with an upper surface and a channel, a dielectric layer disposed over the upper surface, and a diffusion barrier layer disposed over the dielectric layer. The diffusion barrier layer is patterned to include multiple segments. A gate electrode is formed over the semiconductor substrate and is electrically coupled to the channel. A drain opening is spatially separated from a first side of the gate electrode. A drain electrode, which also is electrically coupled to the channel, includes a first portion formed within the drain opening, and a second portion that overlies a segment of the diffusion barrier layer. A conductive field plate between the gate electrode and the drain electrode includes a field plate layer and another segment of the diffusion barrier layer. The drain electrode and the field plate layer may be formed from portions of a same conductive layer.
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3.
公开(公告)号:US12113101B2
公开(公告)日:2024-10-08
申请号:US17369600
申请日:2021-07-07
IPC分类号: H01L29/06 , H01L21/265 , H01L21/266 , H01L21/324 , H01L29/40
CPC分类号: H01L29/0615 , H01L21/26546 , H01L21/266 , H01L21/3245 , H01L29/401 , H01L29/402
摘要: A method for manufacturing a semiconductor device includes: providing a semiconductor substrate; epitaxially growing a first semiconductor layer coupled to the semiconductor substrate; epitaxially growing a second semiconductor layer coupled to the first semiconductor layer, wherein the second semiconductor layer comprises a contact region and a terminal region surrounding the contact region; forming a mask layer on the second semiconductor layer, wherein the mask layer is patterned with a tapered region aligned with the terminal region of the second semiconductor layer; implanting ions into the terminal region of the second semiconductor layer using the mask layer to form a tapered junction termination element in the terminal region of the second semiconductor layer; and forming a contact structure in the contact region of the second semiconductor layer.
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公开(公告)号:US20240332397A1
公开(公告)日:2024-10-03
申请号:US18576324
申请日:2022-01-06
申请人: Analog Devices, Inc.
发明人: James G. Fiorenza , Daniel Piedra
IPC分类号: H01L29/66 , H01L29/20 , H01L29/40 , H01L29/423 , H01L29/778
CPC分类号: H01L29/66462 , H01L29/2003 , H01L29/402 , H01L29/42316 , H01L29/7786
摘要: A gallium nitride (GaN) semiconductor device, such as a field-effect transistor (FET), is described with a design that can enable the semiconductor device to handle high current and high voltage simultaneously. For example, the device can have highly doped n-type N+ regions to ensure low contact resistance and high current. The semiconductor device can have a lightly conducting region next to the drain side of the gate contact, and the device can have a more highly conducting region further from the edge of the drain side of the gate contact. The semiconductor device can handle high current because of the low contact resistance and highly doped drain region but can handle a high electric field because of the lightly doped region near the drain edge of the gate contact. The semiconductor device can be formed in GaN by forming the original N+/N− structure, and then etching a portion of it away, and then regrowing the barrier layer.
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公开(公告)号:US20240332375A1
公开(公告)日:2024-10-03
申请号:US18332795
申请日:2023-06-12
申请人: DB HiTek Co., Ltd.
发明人: Jong Ho LEE
CPC分类号: H01L29/402 , H01L28/20 , H01L29/0607 , H01L29/66681 , H01L29/7816
摘要: Disclosed are a high voltage semiconductor device and a method of manufacturing the same. More particularly, a high voltage semiconductor device and a method of manufacturing the same include a metal field plate, which may be manufactured substantially simultaneously with a thin film resistor (TFR) (e.g., in the same process step[s] or sequence), between a source metal and a gate electrode to improve peak electric field dispersion and breakdown voltage characteristics.
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公开(公告)号:US20240332369A1
公开(公告)日:2024-10-03
申请号:US18193391
申请日:2023-03-30
发明人: Fuchao Wang , Billy Alan Wofford , Ebenezer Eshun , Jungwoo Joh , Dong Seup Lee
IPC分类号: H01L29/20 , H01L21/8252 , H01L27/088 , H01L29/08 , H01L29/40
CPC分类号: H01L29/2003 , H01L21/8252 , H01L27/088 , H01L29/0847 , H01L29/402
摘要: In one example, an integrated circuit comprises a transistor and a metal layer. The transistor has an insulator layer over a substrate that includes gallium nitride (GaN). First and second opening in the insulator layer respectively define a drain region and a source region of the transistor. A gate electrode extends into the insulator layer between the source region and the drain region. The metal layer includes a drain via and a source via. The drain via extends through the first opening to the drain region. The source via extends through the second opening to the source region. A source field plate is in the metal layer. The source field plate extends over the gate electrode and provides a contiguous electrically conductive path to the source region.
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7.
公开(公告)号:US20240332368A1
公开(公告)日:2024-10-03
申请号:US18129457
申请日:2023-03-31
申请人: GaN Systems Inc.
发明人: Vineet Unni , Thomas MacElwee
IPC分类号: H01L29/20 , H01L29/40 , H01L29/66 , H01L29/778
CPC分类号: H01L29/2003 , H01L29/402 , H01L29/66462 , H01L29/7786
摘要: A GaN semiconductor power transistor structure with a stepped gate field plate, and a method of fabrication is disclosed. The stepped gate field plate is formed using contact metal and/or interconnect metal. The stepped structure of the gate field plate is defined by dielectric etching to form openings for the stepped gate field plate, and the dielectric thickness under the gate field plate is sized and stepped to shape appropriately the electric field in the region between the gate and drain. The resulting stepped gate field plate structure is less sensitive to limitations of stepped field plates fabricated by a lift-off metal process.
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公开(公告)号:US20240322033A1
公开(公告)日:2024-09-26
申请号:US18255760
申请日:2021-12-02
申请人: Robert Bosch GmbH
发明人: Dragos Costachescu , Neil Davies
IPC分类号: H01L29/78 , H01L29/10 , H01L29/40 , H01L29/417
CPC分类号: H01L29/7813 , H01L29/1095 , H01L29/402 , H01L29/41725
摘要: A vertical power transistor having front and rear sides. The vertical power transistor includes a drift region that includes a first doping with a first charge carrier type, and a body region that includes a second doping with a second charge carrier type. The body region is situated on the drift region, and includes trenches that extend, starting from the front side, essentially perpendicularly into the drift region. First and second areas are situated between the trenches. The first areas are situated centrally between the trenches, and the second areas are situated between the first areas and the trenches. The first and second areas, starting from the body region, extend essentially perpendicularly into the drift region. The first areas include a third doping with the second charge carrier type, and the second areas include the first doping with the first charge carrier type.
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9.
公开(公告)号:US20240313102A1
公开(公告)日:2024-09-19
申请号:US18596536
申请日:2024-03-05
发明人: Cristina MICCOLI , Ferdinando IUCOLANO , Cristina TRINGALI , Maria Eloisa CASTAGNA , Alessandro CHINI
IPC分类号: H01L29/778 , H01L29/20 , H01L29/40 , H01L29/423 , H01L29/66
CPC分类号: H01L29/7786 , H01L29/2003 , H01L29/402 , H01L29/42316 , H01L29/66462
摘要: An integrated power device includes a heterostructure, having a channel layer and a barrier layer, a source contact, a drain contact, and a gate region, arranged on the barrier layer between the source contact and the drain contact. An insulating field structure is arranged on the barrier layer between the gate region and the drain contact. A field plate extends over the insulating field structure. The insulating field structure includes a first dielectric region made of a first dielectric material on the barrier layer and a second dielectric region made of a second dielectric material, selectively etchable with respect to the first dielectric material on the first dielectric region. On a side of the insulating field structure towards the gate region, the field plate is in contact with the first dielectric region.
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10.
公开(公告)号:US20240274688A1
公开(公告)日:2024-08-15
申请号:US18603994
申请日:2024-03-13
发明人: Zhili ZHANG , Jin RAO , Tao LIU , Haijun LI , Shuiming LI , Ming LU
IPC分类号: H01L29/45 , H01L21/285 , H01L21/768 , H01L23/00 , H01L23/367 , H01L23/373 , H01L23/48 , H01L29/20 , H01L29/40 , H01L29/417 , H01L29/66 , H01L29/778 , H03F3/213
CPC分类号: H01L29/452 , H01L21/28575 , H01L21/76898 , H01L23/3675 , H01L23/3735 , H01L23/481 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L29/2003 , H01L29/401 , H01L29/402 , H01L29/41758 , H01L29/66462 , H01L29/7786 , H01L2224/32225 , H01L2224/45144 , H01L2224/48175 , H01L2224/73265 , H01L2924/1033 , H01L2924/13064 , H01L2924/1421 , H03F3/213
摘要: The present disclosure relates to semiconductor devices, manufacturing methods, a power amplification circuits, and electronic devices. One example semiconductor device includes a substrate, a channel layer and a barrier layer sequentially disposed on the substrate in a stacked manner, a source, a gate, and a drain disposed on the barrier layer, a backside via through a region from the substrate to the barrier layer below the source, and a backside conductive layer covering the backside via and a back surface of the substrate, where the source is in contact with and connected to the backside conductive layer.
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