Method and relative circuit for incrementing, decrementing or two's complementing a bit string
    1.
    发明申请
    Method and relative circuit for incrementing, decrementing or two's complementing a bit string 有权
    用于递增,递减或二进制补码的方法和相关电路

    公开(公告)号:US20040073586A1

    公开(公告)日:2004-04-15

    申请号:US10651075

    申请日:2003-08-28

    CPC classification number: G06F7/5055 G06F7/48 G06F7/49921

    Abstract: A method for incrementing, decrementing or two's complementing a first string of bits includes generating an auxiliary string of bits as a function of the first string, and logically combining the auxiliary string with the first string to generate a corresponding output string. A least significant bit of the auxiliary string is independent from the bits of the first string, and any other bit of the auxiliary string. The method is particularly convenient for generating an overflow flag when the number to be output exceeds the representation interval. An overflow flag is generated by logically combining the most significant bits of the first and auxiliary strings.

    Abstract translation: 用于递增,递减或二进制补码第一比特串的方法包括生成辅助字符串作为第一字符串的函数,并将辅助字符串与第一字符串逻辑组合以生成相应的输出字符串。 辅助字符串的最低有效位与第一个字符串的位和辅助字符串的任何其他位无关。 当要输出的数字超过表示间隔时,该方法特别方便生成溢出标志。 通过逻辑组合第一和辅助字符串的最高有效位来产生溢出标志。

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