公开(公告)号：US09448767B2

公开(公告)日：2016-09-20

申请号：US14192102

申请日：2014-02-27

申请人： Texas Instruments Incorporated

发明人： Timothy D. Anderson ,  Mujibur Rahman ,  Kai Chirca

IPC分类号： G06F7/50 ,  G06F7/57 ,  G06F7/505 ,  G06F7/506

CPC分类号： G06F7/57 ,  G06F7/5055 ,  G06F7/506

摘要： A predictive adder produces the result of incrementing and/or decrementing a sum of A and B by a one-bit constant of the form of the form 2k, where k is a bit position at which the sum is to be incremented or decremented. The predictive adder predicts the ripple portion of bits in the potential sum of the first operand A and the second operand B that would be toggled by incrementing or decrementing the sum A+B by the one-bit constant to generate and indication of the ripple portion of bits in the potential sum. The predictive adder uses the indication of the ripple portion of bits in the potential sum and the carry output generated by evaluating A+B to produce the results of at least one of A+B+2k and A+B−2k.

摘要翻译： 预测加法器产生将形式为2k的1比特常数递增和/或递减A和B的和的结果，其中k是要递增或递减的比特位置。 预测加法器预测第一操作数A和第二操作数B的电位之和的纹波部分，该第一操作数A和第二操作数B将通过将和A + B递增或递减1比特常数来切换，以产生和指示纹波部分 的位数在电位和。 预测加法器使用电位和中的波纹部分的指示和通过评估A + B产生的进位输出来产生A + B + 2k和A + B-2k中的至少一个的结果。

公开(公告)号：US20140181165A1

公开(公告)日：2014-06-26

申请号：US14192102

申请日：2014-02-27

申请人： Texas Instruments Incorporated

发明人： Timothy D. Anderson ,  Mujibur Rahman ,  Kai Chirca

IPC分类号： G06F7/57

CPC分类号： G06F7/57 ,  G06F7/5055 ,  G06F7/506

摘要： A predictive adder produces the result of incrementing and/or decrementing a sum of A and B by a one-bit constant of the form of the form 2k, where k is a bit position at which the sum is to be incremented or decremented. The predictive adder predicts the ripple portion of bits in the potential sum of the first operand A and the second operand B that would be toggled by incrementing or decrementing the sum A+B by the one-bit constant to generate and indication of the ripple portion of bits in the potential sum. The predictive adder uses the indication of the ripple portion of bits in the potential sum and the carry output generated by evaluating A+B to produce the results of at least one of A+B+2k and A+B−2k.

摘要翻译： 预测加法器产生将形式为2k的1比特常数递增和/或递减A和B的和的结果，其中k是要递增或递减的比特位置。 预测加法器预测第一操作数A和第二操作数B的电位之和的纹波部分，该第一操作数A和第二操作数B将通过将和A + B递增或递减1比特常数来切换，以产生和指示波纹部分 的位数在电位和。 预测加法器使用电位和中的波纹部分的指示和通过评估A + B产生的进位输出来产生A + B + 2k和A + B-2k中的至少一个的结果。

公开(公告)号：US08576723B2

公开(公告)日：2013-11-05

申请号：US12271394

申请日：2008-11-14

申请人： Yuen Fai Wong ,  Hui Zhang

发明人： Yuen Fai Wong ,  Hui Zhang

IPC分类号： H04L1/00

CPC分类号： G06F7/5055

摘要： Techniques for incrementing counters in an efficient manner. In one set of embodiments, counter logic circuits are provided that can operate at higher frequencies than existing counter logic circuits, while being capable of being implemented in currently available field programmable gate arrays (FPGAs) or fabricated using currently available process technologies. The counter logic circuits of the present invention may be used to increment statistics counters in network devices that support line speeds of 40 Gbps, 100 Gbps, and greater.

摘要翻译： 以有效的方式增加计数器的技术。 在一组实施例中，提供了可以以比现有计数器逻辑电路更高的频率工作的计数器逻辑电路，同时能够在当前可用的现场可编程门阵列（FPGA）中实现或者使用当前可用的处理技术制造。 本发明的计数器逻辑电路可用于增加支持40Gbps，100Gbps和更高线路速度的网络设备中的统计计数器。

公开(公告)号：US20130290393A1

公开(公告)日：2013-10-31

申请号：US13926918

申请日：2013-06-25

申请人： Deepak K. Singh

发明人： Deepak K. Singh

IPC分类号： G06F7/505

CPC分类号： G06F7/5055

摘要： An incrementor circuit and method for incrementing is provided that computes an output data word by increasing an input data word magnitude by one of several integer values. The incrementor circuit includes a mode increment signal circuit providing a designation of one of the integer values for increasing the input data word magnitude. A single constant incrementor is connected to the mode increment signal circuit and the input data word and provides an intermediate sum by selectively adding a constant to the input data word. A multiplex circuit logically combines selected input data word bit position values with the mode increment signal circuit designation forming logical bit position values and directs selected input data word bit position values, selected logical bit position values, and selected bit position values of the intermediate sum to form the output data word.

摘要翻译： 提供了一种用于递增的递增器电路和方法，其通过将输入数据字幅度增加到几个整数值之一来计算输出数据字。 增量器电路包括模式增量信号电路，其提供用于增加输入数据字幅度的整数值之一的指定。 单个常数增量器连接到模式增量信号电路和输入数据字，并通过选择性地向输入数据字添加常数来提供中间和。 多路复用电路将所选择的输入数据字位位置值与形成逻辑位位置值的模式增量信号电路指定逻辑组合，并将所选择的输入数据字位位置值，所选择的逻辑位位置值和中间和的选定位位置值引导到 形成输出数据字。

公开(公告)号：US20090271592A1

公开(公告)日：2009-10-29

申请号：US12429029

申请日：2009-04-23

申请人： Michael Gottlieb Jensen

发明人： Michael Gottlieb Jensen

IPC分类号： G06F9/30

CPC分类号： G06F9/3851 ,  G06F7/5055 ,  G06F9/30079 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3861 ,  G06F9/3867

摘要： A circuit for selecting one of N requesters in a round-robin fashion is disclosed. The circuit 1-bit left rotatively increments a first addend by a second addend to generate a sum that is ANDed with the inverse of the first addend to generate a 1-hot vector indicating which of the requestors is selected next. The first addend is an N-bit vector where each bit is false if the corresponding requester is requesting access to a shared resource. The second addend is a 1-hot vector indicating the last selected requestor. A multithreading microprocessor dispatch scheduler employs the circuit for N concurrent threads each thread having one of P priorities. The dispatch scheduler generates P N-bit 1-hot round-robin bit vectors, and each thread's priority is used to select the appropriate round-robin bit from P vectors for combination with the thread's priority and an issuable bit to create a dispatch level used to select a thread for instruction dispatching.

摘要翻译： 公开了一种以循环方式选择N个请求者之一的电路。 1位左电路左旋转地增加第二加数的第一加数以产生与第一加数的反相并行的和，以产生指示下一个选择哪个请求者的1-热向量。 第一个加数是一个N位向量，如果相应的请求者请求访问共享资源，则每个位都为假。 第二个加法是指示最后一个选择的请求者的1-hot向量。 多线程微处理器调度调度器使用N个并发线程的电路，每个线程具有P个优先级之一。 调度调度器生成P N位1个热循环比特向量，并且每个线程的优先级用于从P向量中选择适当的循环比例以与线程的优先级组合，并且可发布位以创建使用的调度级别 选择用于指令调度的线程。

公开(公告)号：US07349937B2

公开(公告)日：2008-03-25

申请号：US10695820

申请日：2003-10-30

申请人： Yo-Han Kwon

发明人： Yo-Han Kwon

IPC分类号： G06F7/50

CPC分类号： G06F7/5055

摘要： A fast incrementer using zero detection and an increment method thereof. The incrementer performs a logic combination on an operand, first logic state inclusion information for each b-bit group of the operand, flag information for each b-bit group of the operand, and an increment value, and outputs a whole increment value for the operand.

摘要翻译： 使用零检测的快速增量器及其增量方法。 增量器对操作数执行逻辑组合，对于操作数的每个b位组的第一逻辑状态包含信息，操作数的每个b位组的标志信息和增量值，并且输出用于 操作数

公开(公告)号：USRE39578E1

公开(公告)日：2007-04-17

申请号：US11176885

申请日：2005-07-07

申请人： Wei-Ping Lu

发明人： Wei-Ping Lu

IPC分类号： G06F7/508

CPC分类号： G06F7/5055 ,  G06F7/508 ,  G06F2207/3884

摘要： An incrementer pipelines the generation of carry lookahead signals. Count registers hold a current count of the incrementer. The current count is fed back as inputs to sum logic, which generates sum bits that are latched into the count registers as a next count. All-ones detect logic detects when all lesser-significance bits in the current count are ones. When all lesser bits are ones, the sum logic toggles the count bit to generate the sum bit for that bit position. Pre-carry logic generates pre-carry lookahead signals from the sum bits. The pre-carry lookahead signals are latched into pipelined carry registers. The pipelined carry registers drive pipelined carry lookahead signals to the all-ones detect logic. Thus carry lookahead signals are generated from a prior sum but used in a next clock cycle to generate then next sum.

摘要翻译： 一个增量器管道进位先行信号的产生。 计数寄存器保存增量器的当前计数。 当前计数作为输入反馈到和逻辑，其产生作为下一个计数被锁存到计数寄存器中的和位。 全部检测逻辑检测当前计数中所有较低位的位是否为1。 当所有较小的位都为1时，总和逻辑切换计数位以产生该位位置的和位。 预进位逻辑从和位产生预进位前置信号。 预进位前置信号被锁存到流水线进位寄存器中。 流水线进位寄存器将流水线进位先行信号驱动到全指示检测逻辑。 因此，进位先行信号是从先前的和产生的，但是在下一个时钟周期中使用，以产生下一个和。

公开(公告)号：US07203714B1

公开(公告)日：2007-04-10

申请号：US09522470

申请日：2000-03-09

申请人： Hiroshi Katakura ,  Yasuhiko Nakashima

发明人： Hiroshi Katakura ,  Yasuhiko Nakashima

IPC分类号： G06F15/00

CPC分类号： G06F7/026 ,  G06F7/5055 ,  G06F7/506 ,  H03K17/693 ,  H03K19/20

摘要： A CMOS logic circuit is disclosed wherein the number of kinds of basic parts is suppressed to five to allow designing of a circuit which operates at a high speed and repetitiveness of wiring lines is increased to allow designing of a circuit which is simple in circuit scale and high in expandability and besides the time required for adjustment of components is reduced significantly to reduce the man-hours for arrangement significantly to reduce the man-hours for development significantly and the same basic parts are used so as to achieve augmentation of the yield and promote reduction of the production cost.

摘要翻译： 公开了一种CMOS逻辑电路，其中基本部件的种类数量被抑制到五个以允许设计高速工作的电路，并且增加布线的重复性以允许设计电路规模简单的电路， 可扩展性高，除了组件调整所需时间显着减少，大大减少了安排工作时间，大大减少了开发工时，同时使用了相同的基本部件，从而提高了产量和促进 降低生产成本。

公开(公告)号：US20050193051A1

公开(公告)日：2005-09-01

申请号：US11115149

申请日：2005-04-27

申请人： Hiroshi Katakura ,  Yasuhiko Nakashima

发明人： Hiroshi Katakura ,  Yasuhiko Nakashima

IPC分类号： G06F7/50 ,  G06F7/02 ,  G06F7/42 ,  G06F7/501 ,  G06F7/505 ,  G06F7/506 ,  G06F7/508 ,  H03K17/693 ,  H03K19/0948 ,  H03K19/20

CPC分类号： G06F7/026 ,  G06F7/5055 ,  G06F7/506 ,  H03K17/693 ,  H03K19/20

摘要： A CMOS logic circuit is disclosed wherein the number of kinds of basic parts is suppressed to five to allow designing of a circuit which operates at a high speed and repetitiveness of wiring lines is increased to allow designing of a circuit which is simple in circuit scale and high in expandability and besides the time required for adjustment of components is reduced significantly to reduce the man-hours for arrangement significantly to reduce the man-hours for development significantly and the same basic parts are used so as to achieve augmentation of the yield and promote reduction of the production cost. A basic cell of the CMOS logic circuit includes a first inversion section for inverting a first input signal having one of positive logic and negative logic and outputting the inverted signal, a second inversion section for inverting a second input signal having the other of the positive logic and the negative logic and outputting the inverted signal, and a transmission section for selectively outputting one of the output of the first inversion section and the output of the second inversion section in accordance with a logical value which depends upon an externally controllable selection signal and an inverted signal of the selection signal.

摘要翻译： 公开了一种CMOS逻辑电路，其中基本部件的种类数量被抑制到五个以允许设计高速工作的电路，并且增加布线的重复性以允许设计电路规模简单的电路， 可扩展性高，除了组件调整所需时间显着减少，大大减少了安排工作时间，大大减少了开发工时，同时使用了相同的基本部件，从而提高了产量和促进 降低生产成本。 CMOS逻辑电路的基本单元包括第一反相部分，用于反相具有正逻辑和负逻辑之一的第一输入信号并输出​​反相信号;第二反相部分，用于反相具有正逻辑中另一个的第二输入信号 和负逻辑并输出反相信号;以及发送部分，用于根据取决于外部可控选择信号的逻辑值和第二反转部分的输出，选择性地输出第一反转部分的输出和第二反转部分的输出之一 反相信号的选择信号。

公开(公告)号：US06772090B2

公开(公告)日：2004-08-03

申请号：US09769679

申请日：2001-01-25

申请人： Brendon Hutton ,  Fanie Duvenhage

发明人： Brendon Hutton ,  Fanie Duvenhage

IPC分类号： G01C2200

CPC分类号： G06F7/5055 ,  G01B3/12 ,  G01C22/02

摘要： An improved vehicle odometer is provided with an encoder and a microcontroller. The encoder has a unique key that configures an encryption algorithm. The encryption algorithm can be in the form of circuitry or software or any combination there between. The encoder receives a increment signal from the vehicle indicating that the vehicle has traveled a pre-determined distance. The encoder then increments the odometer-related value and then encrypts it with the encryption algorithm. The encoder then wraps the encrypted odometer-related value into a data packet with a serial number. Only a suitably equipped computing device, such as a microcontroller, identify and correctly decrypt and process the encrypted odometer-related value, thereby preventing the tampering of the vehicle's odometer.

摘要翻译： 改进的车辆里程表设置有编码器和微控制器。 编码器具有配置加密算法的唯一密钥。 加密算法可以是电路或软件的形式或其间的任何组合。 编码器接收来自车辆的增量信号，指示车辆行驶了预定距离。 然后，编码器增加里程表相关值，然后使用加密算法对其进行加密。 然后，编码器将加密的里程表相关值包装成具有序列号的数据分组。 只有适当配备的计算设备（如微控制器）才能识别并正确解密和处理加密的里程计相关值，从而防止车辆里程表的篡改。