公开(公告)号：US20020063307A1

公开(公告)日：2002-05-30

申请号：US09991555

申请日：2001-11-21

Applicant: STMicroelectronics S.r.I.

Inventor： Davide Patti

IPC: H01L027/01 ,  H01L027/12 ,  H01L031/0392 ,  H01L029/76 ,  H01L031/062 ,  H01L029/94 ,  H01L031/119 ,  H01L021/20 ,  H01L029/00 ,  H01L023/62 ,  H01L031/113 ,  H01L027/082 ,  H01L027/102 ,  H01L029/70 ,  H01L031/11

CPC classification number: H01L28/20 ,  H01L27/0802 ,  H01L29/8605

Abstract: A structure for a semiconductor resistive element, applicable in particular to power components, having a high concentration substrate of the n type, a first epitaxial layer of the n type, a region of the p type arranged on said first epitaxial layer so to form the resistive element proper, a second epitaxial layer of n type grown on said first epitaxial layer to make the region of the p type a buried region, and an additional layer of the n type with a higher concentration with respect to the second epitaxial level, positioned on the embedded region. Low resistivity regions of the p type adapted to make low resistivity deep contacts for the resistor are provided. The buried region can be made either with a development that is substantially uniform in its main direction of extension or so to present, at on part of its length, a structure of adjacent subregions in marginal continuity. In this way, either a resistive element presenting a substantially linear performance in all ranges of applied voltage or a resistive element presenting a marked increase of the resistance value as the applied voltage increases can be made. This all with the additional possibility of selectively varying the resistance value demonstrated before the increase.

Abstract translation: 一种用于半导体电阻元件的结构，特别适用于具有n型高浓度衬底，n型第一外延层，布置在所述第一外延层上的p型区域的功率元件，从而形成 电阻元件本体，在所述第一外延层上生长以使p型区域成为掩埋区域的n型第二外延层和相对于第二外延级别具有较高浓度的n型附加层，定位 在嵌入式区域。 提供适于为电阻器制造低电阻率深触点的p型低电阻率区域。 掩埋区域可以通过在其主要延伸方向上基本均匀的发展来实现，或者在其长度的一部分上呈现边缘连续性的相邻子区域的结构。 以这种方式，可以在所施加的电压的所有范围内呈现基本上线性的电阻元件，或者施加的电压增加时呈现电阻值的显着增加的电阻元件。 这一切都具有选择性地改变在增加之前显示的电阻值的附加可能性。