公开(公告)号：US20030032244A1

公开(公告)日：2003-02-13

申请号：US10261987

申请日：2002-10-01

Applicant: STMicroelectronics S.r.I.

Inventor： Daniela Peschiaroli ,  Alfonso Maurelli ,  Elisabetta Palumbo ,  Fausto Piazza

IPC: H01L021/336

CPC classification number: H01L27/11526 ,  H01L27/1052 ,  H01L27/11541

Abstract: A method for manufacturing an integrated circuit having a memory device and a logic circuit includes forming a plurality of first transistors in a first portion of a semiconductor substrate, a plurality of second transistors in a second portion of the semiconductor substrate, and a plurality of memory cells in a third portion of the semiconductor substrate. A matrix mask used for selectively removing a dielectric layer from the first and third portions of the semiconductor substrate allows dielectric to remain on a floating gate of the plurality of memory cells and on the gate electrodes of the plurality of first transistors. A control gate is then formed on the floating gate, which is separated by the dielectric. Portions of the gate electrodes for the plurality of first transistors are left free so that contact is made with the transistors.